Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
577 lines
19 KiB
C++
577 lines
19 KiB
C++
/*
|
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
/** @file
|
|
* Emulation of the Tsunami CChip CSRs
|
|
*/
|
|
|
|
#include <deque>
|
|
#include <string>
|
|
#include <vector>
|
|
|
|
#include "base/trace.hh"
|
|
#include "dev/tsunami_cchip.hh"
|
|
#include "dev/tsunamireg.h"
|
|
#include "dev/tsunami.hh"
|
|
#include "mem/bus/bus.hh"
|
|
#include "mem/bus/pio_interface.hh"
|
|
#include "mem/bus/pio_interface_impl.hh"
|
|
#include "mem/functional/memory_control.hh"
|
|
#include "cpu/intr_control.hh"
|
|
#include "sim/builder.hh"
|
|
#include "sim/system.hh"
|
|
|
|
using namespace std;
|
|
|
|
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
|
|
MemoryController *mmu, HierParams *hier, Bus* bus,
|
|
Tick pio_latency)
|
|
: PioDevice(name, t), addr(a), tsunami(t)
|
|
{
|
|
mmu->add_child(this, RangeSize(addr, size));
|
|
|
|
if (bus) {
|
|
pioInterface = newPioInterface(name, hier, bus, this,
|
|
&TsunamiCChip::cacheAccess);
|
|
pioInterface->addAddrRange(RangeSize(addr, size));
|
|
pioLatency = pio_latency * bus->clockRate;
|
|
}
|
|
|
|
drir = 0;
|
|
ipint = 0;
|
|
itint = 0;
|
|
|
|
for (int x = 0; x < Tsunami::Max_CPUs; x++)
|
|
{
|
|
dim[x] = 0;
|
|
dir[x] = 0;
|
|
}
|
|
|
|
//Put back pointer in tsunami
|
|
tsunami->cchip = this;
|
|
}
|
|
|
|
Fault
|
|
TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
|
|
{
|
|
DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
|
|
|
|
Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
|
|
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
|
|
|
|
ExecContext *xc = req->xc;
|
|
|
|
switch (req->size) {
|
|
|
|
case sizeof(uint64_t):
|
|
if (daddr & TSDEV_CC_BDIMS)
|
|
{
|
|
*(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
|
|
return No_Fault;
|
|
}
|
|
|
|
if (daddr & TSDEV_CC_BDIRS)
|
|
{
|
|
*(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
|
|
return No_Fault;
|
|
}
|
|
|
|
switch(regnum) {
|
|
case TSDEV_CC_CSR:
|
|
*(uint64_t*)data = 0x0;
|
|
return No_Fault;
|
|
case TSDEV_CC_MTR:
|
|
panic("TSDEV_CC_MTR not implemeted\n");
|
|
return No_Fault;
|
|
case TSDEV_CC_MISC:
|
|
*(uint64_t*)data = (ipint << 8) & 0xF |
|
|
(itint << 4) & 0xF |
|
|
(xc->cpu_id & 0x3);
|
|
return No_Fault;
|
|
case TSDEV_CC_AAR0:
|
|
case TSDEV_CC_AAR1:
|
|
case TSDEV_CC_AAR2:
|
|
case TSDEV_CC_AAR3:
|
|
*(uint64_t*)data = 0;
|
|
return No_Fault;
|
|
case TSDEV_CC_DIM0:
|
|
*(uint64_t*)data = dim[0];
|
|
return No_Fault;
|
|
case TSDEV_CC_DIM1:
|
|
*(uint64_t*)data = dim[1];
|
|
return No_Fault;
|
|
case TSDEV_CC_DIM2:
|
|
*(uint64_t*)data = dim[2];
|
|
return No_Fault;
|
|
case TSDEV_CC_DIM3:
|
|
*(uint64_t*)data = dim[3];
|
|
return No_Fault;
|
|
case TSDEV_CC_DIR0:
|
|
*(uint64_t*)data = dir[0];
|
|
return No_Fault;
|
|
case TSDEV_CC_DIR1:
|
|
*(uint64_t*)data = dir[1];
|
|
return No_Fault;
|
|
case TSDEV_CC_DIR2:
|
|
*(uint64_t*)data = dir[2];
|
|
return No_Fault;
|
|
case TSDEV_CC_DIR3:
|
|
*(uint64_t*)data = dir[3];
|
|
return No_Fault;
|
|
case TSDEV_CC_DRIR:
|
|
*(uint64_t*)data = drir;
|
|
return No_Fault;
|
|
case TSDEV_CC_PRBEN:
|
|
panic("TSDEV_CC_PRBEN not implemented\n");
|
|
return No_Fault;
|
|
case TSDEV_CC_IIC0:
|
|
case TSDEV_CC_IIC1:
|
|
case TSDEV_CC_IIC2:
|
|
case TSDEV_CC_IIC3:
|
|
panic("TSDEV_CC_IICx not implemented\n");
|
|
return No_Fault;
|
|
case TSDEV_CC_MPR0:
|
|
case TSDEV_CC_MPR1:
|
|
case TSDEV_CC_MPR2:
|
|
case TSDEV_CC_MPR3:
|
|
panic("TSDEV_CC_MPRx not implemented\n");
|
|
return No_Fault;
|
|
case TSDEV_CC_IPIR:
|
|
*(uint64_t*)data = ipint;
|
|
return No_Fault;
|
|
case TSDEV_CC_ITIR:
|
|
*(uint64_t*)data = itint;
|
|
return No_Fault;
|
|
default:
|
|
panic("default in cchip read reached, accessing 0x%x\n");
|
|
} // uint64_t
|
|
|
|
break;
|
|
case sizeof(uint32_t):
|
|
if (regnum == TSDEV_CC_DRIR) {
|
|
warn("accessing DRIR with 32 bit read, "
|
|
"hopefully your just reading this for timing");
|
|
*(uint32_t*)data = drir;
|
|
} else
|
|
panic("invalid access size(?) for tsunami register!\n");
|
|
return No_Fault;
|
|
case sizeof(uint16_t):
|
|
case sizeof(uint8_t):
|
|
default:
|
|
panic("invalid access size(?) for tsunami register!\n");
|
|
}
|
|
DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size);
|
|
|
|
return No_Fault;
|
|
}
|
|
|
|
Fault
|
|
TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
|
|
{
|
|
DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
|
|
req->vaddr, *(uint64_t*)data, req->size);
|
|
|
|
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
|
|
Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
|
|
|
|
bool supportedWrite = false;
|
|
|
|
switch (req->size) {
|
|
|
|
case sizeof(uint64_t):
|
|
if (daddr & TSDEV_CC_BDIMS)
|
|
{
|
|
int number = (daddr >> 4) & 0x3F;
|
|
|
|
uint64_t bitvector;
|
|
uint64_t olddim;
|
|
uint64_t olddir;
|
|
|
|
olddim = dim[number];
|
|
olddir = dir[number];
|
|
dim[number] = *(uint64_t*)data;
|
|
dir[number] = dim[number] & drir;
|
|
for(int x = 0; x < Tsunami::Max_CPUs; x++)
|
|
{
|
|
bitvector = ULL(1) << x;
|
|
// Figure out which bits have changed
|
|
if ((dim[number] & bitvector) != (olddim & bitvector))
|
|
{
|
|
// The bit is now set and it wasn't before (set)
|
|
if((dim[number] & bitvector) && (dir[number] & bitvector))
|
|
{
|
|
tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
|
|
DPRINTF(Tsunami, "dim write resulting in posting dir"
|
|
" interrupt to cpu %d\n", number);
|
|
}
|
|
else if ((olddir & bitvector) &&
|
|
!(dir[number] & bitvector))
|
|
{
|
|
// The bit was set and now its now clear and
|
|
// we were interrupting on that bit before
|
|
tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
|
|
DPRINTF(Tsunami, "dim write resulting in clear"
|
|
" dir interrupt to cpu %d\n", number);
|
|
|
|
}
|
|
|
|
|
|
}
|
|
}
|
|
return No_Fault;
|
|
}
|
|
|
|
switch(regnum) {
|
|
case TSDEV_CC_CSR:
|
|
panic("TSDEV_CC_CSR write\n");
|
|
return No_Fault;
|
|
case TSDEV_CC_MTR:
|
|
panic("TSDEV_CC_MTR write not implemented\n");
|
|
return No_Fault;
|
|
case TSDEV_CC_MISC:
|
|
uint64_t ipreq;
|
|
ipreq = (*(uint64_t*)data >> 12) & 0xF;
|
|
//If it is bit 12-15, this is an IPI post
|
|
if (ipreq) {
|
|
reqIPI(ipreq);
|
|
supportedWrite = true;
|
|
}
|
|
|
|
//If it is bit 8-11, this is an IPI clear
|
|
uint64_t ipintr;
|
|
ipintr = (*(uint64_t*)data >> 8) & 0xF;
|
|
if (ipintr) {
|
|
clearIPI(ipintr);
|
|
supportedWrite = true;
|
|
}
|
|
|
|
//If it is the 4-7th bit, clear the RTC interrupt
|
|
uint64_t itintr;
|
|
itintr = (*(uint64_t*)data >> 4) & 0xF;
|
|
if (itintr) {
|
|
clearITI(itintr);
|
|
supportedWrite = true;
|
|
}
|
|
|
|
// ignore NXMs
|
|
if (*(uint64_t*)data & 0x10000000)
|
|
supportedWrite = true;
|
|
|
|
if(!supportedWrite)
|
|
panic("TSDEV_CC_MISC write not implemented\n");
|
|
|
|
return No_Fault;
|
|
case TSDEV_CC_AAR0:
|
|
case TSDEV_CC_AAR1:
|
|
case TSDEV_CC_AAR2:
|
|
case TSDEV_CC_AAR3:
|
|
panic("TSDEV_CC_AARx write not implemeted\n");
|
|
return No_Fault;
|
|
case TSDEV_CC_DIM0:
|
|
case TSDEV_CC_DIM1:
|
|
case TSDEV_CC_DIM2:
|
|
case TSDEV_CC_DIM3:
|
|
int number;
|
|
if(regnum == TSDEV_CC_DIM0)
|
|
number = 0;
|
|
else if(regnum == TSDEV_CC_DIM1)
|
|
number = 1;
|
|
else if(regnum == TSDEV_CC_DIM2)
|
|
number = 2;
|
|
else
|
|
number = 3;
|
|
|
|
uint64_t bitvector;
|
|
uint64_t olddim;
|
|
uint64_t olddir;
|
|
|
|
olddim = dim[number];
|
|
olddir = dir[number];
|
|
dim[number] = *(uint64_t*)data;
|
|
dir[number] = dim[number] & drir;
|
|
for(int x = 0; x < 64; x++)
|
|
{
|
|
bitvector = ULL(1) << x;
|
|
// Figure out which bits have changed
|
|
if ((dim[number] & bitvector) != (olddim & bitvector))
|
|
{
|
|
// The bit is now set and it wasn't before (set)
|
|
if((dim[number] & bitvector) && (dir[number] & bitvector))
|
|
{
|
|
tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
|
|
DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
|
|
}
|
|
else if ((olddir & bitvector) &&
|
|
!(dir[number] & bitvector))
|
|
{
|
|
// The bit was set and now its now clear and
|
|
// we were interrupting on that bit before
|
|
tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
|
|
DPRINTF(Tsunami, "dim write resulting in clear"
|
|
" dir interrupt to cpu %d\n",
|
|
x);
|
|
|
|
}
|
|
|
|
|
|
}
|
|
}
|
|
return No_Fault;
|
|
case TSDEV_CC_DIR0:
|
|
case TSDEV_CC_DIR1:
|
|
case TSDEV_CC_DIR2:
|
|
case TSDEV_CC_DIR3:
|
|
panic("TSDEV_CC_DIR write not implemented\n");
|
|
case TSDEV_CC_DRIR:
|
|
panic("TSDEV_CC_DRIR write not implemented\n");
|
|
case TSDEV_CC_PRBEN:
|
|
panic("TSDEV_CC_PRBEN write not implemented\n");
|
|
case TSDEV_CC_IIC0:
|
|
case TSDEV_CC_IIC1:
|
|
case TSDEV_CC_IIC2:
|
|
case TSDEV_CC_IIC3:
|
|
panic("TSDEV_CC_IICx write not implemented\n");
|
|
case TSDEV_CC_MPR0:
|
|
case TSDEV_CC_MPR1:
|
|
case TSDEV_CC_MPR2:
|
|
case TSDEV_CC_MPR3:
|
|
panic("TSDEV_CC_MPRx write not implemented\n");
|
|
case TSDEV_CC_IPIR:
|
|
clearIPI(*(uint64_t*)data);
|
|
return No_Fault;
|
|
case TSDEV_CC_ITIR:
|
|
clearITI(*(uint64_t*)data);
|
|
return No_Fault;
|
|
case TSDEV_CC_IPIQ:
|
|
reqIPI(*(uint64_t*)data);
|
|
return No_Fault;
|
|
default:
|
|
panic("default in cchip read reached, accessing 0x%x\n");
|
|
}
|
|
|
|
break;
|
|
case sizeof(uint32_t):
|
|
case sizeof(uint16_t):
|
|
case sizeof(uint8_t):
|
|
default:
|
|
panic("invalid access size(?) for tsunami register!\n");
|
|
}
|
|
|
|
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
|
|
|
|
return No_Fault;
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::clearIPI(uint64_t ipintr)
|
|
{
|
|
int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(numcpus <= Tsunami::Max_CPUs);
|
|
|
|
if (ipintr) {
|
|
for (int cpunum=0; cpunum < numcpus; cpunum++) {
|
|
// Check each cpu bit
|
|
uint64_t cpumask = ULL(1) << cpunum;
|
|
if (ipintr & cpumask) {
|
|
// Check if there is a pending ipi
|
|
if (ipint & cpumask) {
|
|
ipint &= ~cpumask;
|
|
tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
|
|
DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
|
|
}
|
|
else
|
|
warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
panic("Big IPI Clear, but not processors indicated\n");
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::clearITI(uint64_t itintr)
|
|
{
|
|
int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(numcpus <= Tsunami::Max_CPUs);
|
|
|
|
if (itintr) {
|
|
for (int i=0; i < numcpus; i++) {
|
|
uint64_t cpumask = ULL(1) << i;
|
|
if (itintr & cpumask & itint) {
|
|
tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
|
|
itint &= ~cpumask;
|
|
DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
panic("Big ITI Clear, but not processors indicated\n");
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::reqIPI(uint64_t ipreq)
|
|
{
|
|
int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(numcpus <= Tsunami::Max_CPUs);
|
|
|
|
if (ipreq) {
|
|
for (int cpunum=0; cpunum < numcpus; cpunum++) {
|
|
// Check each cpu bit
|
|
uint64_t cpumask = ULL(1) << cpunum;
|
|
if (ipreq & cpumask) {
|
|
// Check if there is already an ipi (bits 8:11)
|
|
if (!(ipint & cpumask)) {
|
|
ipint |= cpumask;
|
|
tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
|
|
DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
|
|
}
|
|
else
|
|
warn("post IPI for CPU=%d, but IPI already\n", cpunum);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
panic("Big IPI Request, but not processors indicated\n");
|
|
}
|
|
|
|
|
|
void
|
|
TsunamiCChip::postRTC()
|
|
{
|
|
int size = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
|
|
for (int i = 0; i < size; i++) {
|
|
uint64_t cpumask = ULL(1) << i;
|
|
if (!(cpumask & itint)) {
|
|
itint |= cpumask;
|
|
tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
|
|
DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::postDRIR(uint32_t interrupt)
|
|
{
|
|
uint64_t bitvector = ULL(1) << interrupt;
|
|
uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
drir |= bitvector;
|
|
|
|
for(int i=0; i < size; i++) {
|
|
dir[i] = dim[i] & drir;
|
|
if (dim[i] & bitvector) {
|
|
tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
|
|
DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
|
|
"interrupt %d\n",i, interrupt);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::clearDRIR(uint32_t interrupt)
|
|
{
|
|
uint64_t bitvector = ULL(1) << interrupt;
|
|
uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
|
|
if (drir & bitvector)
|
|
{
|
|
drir &= ~bitvector;
|
|
for(int i=0; i < size; i++) {
|
|
if (dir[i] & bitvector) {
|
|
tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
|
|
DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
|
|
"interrupt %d\n",i, interrupt);
|
|
|
|
}
|
|
dir[i] = dim[i] & drir;
|
|
}
|
|
}
|
|
else
|
|
DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
|
|
}
|
|
|
|
Tick
|
|
TsunamiCChip::cacheAccess(MemReqPtr &req)
|
|
{
|
|
return curTick + pioLatency;
|
|
}
|
|
|
|
|
|
void
|
|
TsunamiCChip::serialize(std::ostream &os)
|
|
{
|
|
SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
|
|
SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
|
|
SERIALIZE_SCALAR(ipint);
|
|
SERIALIZE_SCALAR(itint);
|
|
SERIALIZE_SCALAR(drir);
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
|
|
UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
|
|
UNSERIALIZE_SCALAR(ipint);
|
|
UNSERIALIZE_SCALAR(itint);
|
|
UNSERIALIZE_SCALAR(drir);
|
|
}
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
SimObjectParam<Tsunami *> tsunami;
|
|
SimObjectParam<MemoryController *> mmu;
|
|
Param<Addr> addr;
|
|
SimObjectParam<Bus*> io_bus;
|
|
Param<Tick> pio_latency;
|
|
SimObjectParam<HierParams *> hier;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
INIT_PARAM(tsunami, "Tsunami"),
|
|
INIT_PARAM(mmu, "Memory Controller"),
|
|
INIT_PARAM(addr, "Device Address"),
|
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
CREATE_SIM_OBJECT(TsunamiCChip)
|
|
{
|
|
return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier,
|
|
io_bus, pio_latency);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
|