Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
187 lines
6.7 KiB
C++
187 lines
6.7 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_SINICREG_HH__
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#define __DEV_SINICREG_HH__
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#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL)
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#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL)
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#define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
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static const uint32_t NAME##_width = WIDTH; \
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static const uint32_t NAME##_offset = OFFSET; \
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static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
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static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
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static inline uint32_t get_##NAME(uint32_t reg) \
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{ return (reg & NAME) >> OFFSET; } \
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static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
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{ return (reg & ~NAME) | ((val << OFFSET) & NAME); }
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#define __SINIC_VAL64(NAME, OFFSET, WIDTH) \
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static const uint64_t NAME##_width = WIDTH; \
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static const uint64_t NAME##_offset = OFFSET; \
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static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \
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static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET; \
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static inline uint64_t get_##NAME(uint64_t reg) \
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{ return (reg & NAME) >> OFFSET; } \
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static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
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{ return (reg & ~NAME) | ((val << OFFSET) & NAME); }
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namespace Sinic {
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namespace Regs {
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// Registers
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__SINIC_REG32(Config, 0x00); // 32: configuration register
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__SINIC_REG32(RxMaxCopy, 0x04); // 32: max rx copy
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__SINIC_REG32(TxMaxCopy, 0x08); // 32: max tx copy
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__SINIC_REG32(RxThreshold, 0x0c); // 32: receive fifo threshold
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__SINIC_REG32(TxThreshold, 0x10); // 32: transmit fifo threshold
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__SINIC_REG32(IntrStatus, 0x14); // 32: interrupt status
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__SINIC_REG32(IntrMask, 0x18); // 32: interrupt mask
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__SINIC_REG32(RxData, 0x20); // 64: receive data
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__SINIC_REG32(RxDone, 0x28); // 64: receive done
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__SINIC_REG32(RxWait, 0x30); // 64: receive done (busy wait)
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__SINIC_REG32(TxData, 0x38); // 64: transmit data
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__SINIC_REG32(TxDone, 0x40); // 64: transmit done
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__SINIC_REG32(TxWait, 0x48); // 64: transmit done (busy wait)
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__SINIC_REG32(HwAddr, 0x50); // 64: mac address
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__SINIC_REG32(Size, 0x58);
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// Config register bits
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__SINIC_VAL32(Config_Reset, 31, 1); // reset chip
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__SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter
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__SINIC_VAL32(Config_Vlan, 6, 1); // enable vlan tagging
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__SINIC_VAL32(Config_Virtual, 5, 1); // enable virtual addressing
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__SINIC_VAL32(Config_Desc, 4, 1); // enable tx/rx descriptors
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__SINIC_VAL32(Config_Poll, 3, 1); // enable polling
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__SINIC_VAL32(Config_IntEn, 2, 1); // enable interrupts
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__SINIC_VAL32(Config_TxEn, 1, 1); // enable transmit
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__SINIC_VAL32(Config_RxEn, 0, 1); // enable receive
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// Interrupt register bits
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__SINIC_VAL32(Intr_TxFifo, 5, 1); // Fifo oflow/uflow/threshold
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__SINIC_VAL32(Intr_TxData, 4, 1); // DMA Completed w/ interrupt
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__SINIC_VAL32(Intr_TxDone, 3, 1); // Packet transmitted
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__SINIC_VAL32(Intr_RxFifo, 2, 1); // Fifo oflow/uflow/threshold
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__SINIC_VAL32(Intr_RxData, 1, 1); // DMA Completed w/ interrupt
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__SINIC_VAL32(Intr_RxDone, 0, 1); // Packet received
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__SINIC_REG32(Intr_All, 0x3f);
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__SINIC_REG32(Intr_NoDelay, 0x24);
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__SINIC_REG32(Intr_Res, ~0x3f);
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// RX Data Description
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__SINIC_VAL64(RxData_Len, 40, 20); // 0 - 1M
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__SINIC_VAL64(RxData_Addr, 0, 40); // Address 1TB
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// TX Data Description
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__SINIC_VAL64(TxData_More, 63, 1);
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__SINIC_VAL64(TxData_Checksum, 62, 1);
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__SINIC_VAL64(TxData_Len, 40, 20); // 0 - 1M
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__SINIC_VAL64(TxData_Addr, 0, 40); // Address 1TB
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// RX Done/Busy Information
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__SINIC_VAL64(RxDone_Complete, 63, 1);
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__SINIC_VAL64(RxDone_IpPacket, 45, 1);
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__SINIC_VAL64(RxDone_TcpPacket, 44, 1);
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__SINIC_VAL64(RxDone_UdpPacket, 43, 1);
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__SINIC_VAL64(RxDone_IpError, 42, 1);
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__SINIC_VAL64(RxDone_TcpError, 41, 1);
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__SINIC_VAL64(RxDone_UdpError, 40, 1);
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__SINIC_VAL64(RxDone_More, 32, 1);
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__SINIC_VAL64(RxDone_FifoLen, 20, 8); // up to 255 packets
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__SINIC_VAL64(RxDone_CopyLen, 0, 20); // up to 256k
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// TX Done/Busy Information
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__SINIC_VAL64(TxDone_Complete, 63, 1);
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__SINIC_VAL64(TxDone_FifoLen, 20, 8); // up to 255 packets
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__SINIC_VAL64(TxDone_CopyLen, 0, 20); // up to 256k
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inline int
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regSize(int offset)
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{
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static const char sizes[] = {
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4,
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4,
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4,
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4,
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4,
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4,
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4,
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0,
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8, 0,
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8, 0,
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8, 0,
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8, 0,
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8, 0,
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8, 0,
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8, 0
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};
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if (offset & 0x3)
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return 0;
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if (offset >= Size)
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return 0;
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return sizes[offset / 4];
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}
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inline const char *
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regName(int offset)
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{
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static const char *names[] = {
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"Config",
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"RxMaxCopy",
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"TxMaxCopy",
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"RxThreshold",
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"TxThreshold",
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"IntrStatus",
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"IntrMask",
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"invalid",
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"RxData", "invalid",
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"RxDone", "invalid",
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"RxWait", "invalid",
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"TxData", "invalid",
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"TxDone", "invalid",
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"TxWait", "invalid",
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"HwAddr", "invalid"
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};
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if (offset & 0x3)
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return "invalid";
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if (offset >= Size)
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return "invalid";
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return names[offset / 4];
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}
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/* namespace Regs */ }
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/* namespace Sinic */ }
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#endif // __DEV_SINICREG_HH__
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