Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
415 lines
9.1 KiB
C++
415 lines
9.1 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Implements the user interface to a serial console
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*/
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#include <sys/ioctl.h>
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#include <sys/termios.h>
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#include <sys/types.h>
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#include <errno.h>
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#include <poll.h>
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#include <unistd.h>
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#include <iostream>
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#include <fstream>
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#include <sstream>
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#include <string>
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#include "base/misc.hh"
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#include "base/output.hh"
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#include "base/socket.hh"
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#include "base/trace.hh"
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#include "dev/platform.hh"
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#include "dev/simconsole.hh"
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#include "dev/uart.hh"
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#include "mem/functional/memory_control.hh"
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#include "sim/builder.hh"
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using namespace std;
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////////////////////////////////////////////////////////////////////////
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//
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//
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SimConsole::Event::Event(SimConsole *c, int fd, int e)
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: PollEvent(fd, e), cons(c)
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{
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}
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void
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SimConsole::Event::process(int revent)
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{
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if (revent & POLLIN)
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cons->data();
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else if (revent & POLLNVAL)
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cons->detach();
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}
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SimConsole::SimConsole(const string &name, ostream *os, int num)
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: SimObject(name), event(NULL), number(num), in_fd(-1), out_fd(-1),
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listener(NULL), txbuf(16384), rxbuf(16384), outfile(os)
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#if TRACING_ON == 1
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, linebuf(16384)
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#endif
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{
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if (outfile)
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outfile->setf(ios::unitbuf);
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}
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SimConsole::~SimConsole()
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{
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close();
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}
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void
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SimConsole::close()
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{
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if (in_fd != -1)
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::close(in_fd);
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if (out_fd != in_fd && out_fd != -1)
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::close(out_fd);
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}
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void
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SimConsole::attach(int in, int out, ConsoleListener *l)
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{
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in_fd = in;
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out_fd = out;
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listener = l;
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event = new Event(this, in, POLLIN);
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pollQueue.schedule(event);
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stringstream stream;
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ccprintf(stream, "==== m5 slave console: Console %d ====", number);
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// we need an actual carriage return followed by a newline for the
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// terminal
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stream << "\r\n";
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write((const uint8_t *)stream.str().c_str(), stream.str().size());
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DPRINTFN("attach console %d\n", number);
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txbuf.readall(out);
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}
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void
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SimConsole::detach()
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{
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close();
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in_fd = -1;
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out_fd = -1;
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pollQueue.remove(event);
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if (listener) {
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listener->add(this);
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listener = NULL;
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}
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DPRINTFN("detach console %d\n", number);
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}
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void
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SimConsole::data()
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{
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uint8_t buf[1024];
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int len;
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len = read(buf, sizeof(buf));
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if (len) {
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rxbuf.write((char *)buf, len);
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// Inform the UART there is data available
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uart->dataAvailable();
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}
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}
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size_t
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SimConsole::read(uint8_t *buf, size_t len)
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{
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if (in_fd < 0)
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panic("Console not properly attached.\n");
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size_t ret;
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do {
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ret = ::read(in_fd, buf, len);
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} while (ret == -1 && errno == EINTR);
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if (ret < 0)
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DPRINTFN("Read failed.\n");
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if (ret <= 0) {
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detach();
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return 0;
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}
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return ret;
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}
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// Console output.
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size_t
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SimConsole::write(const uint8_t *buf, size_t len)
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{
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if (out_fd < 0)
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panic("Console not properly attached.\n");
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size_t ret;
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for (;;) {
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ret = ::write(out_fd, buf, len);
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if (ret >= 0)
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break;
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if (errno != EINTR)
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detach();
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}
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return ret;
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}
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#define MORE_PENDING (ULL(1) << 61)
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#define RECEIVE_SUCCESS (ULL(0) << 62)
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#define RECEIVE_NONE (ULL(2) << 62)
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#define RECEIVE_ERROR (ULL(3) << 62)
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bool
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SimConsole::in(uint8_t &c)
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{
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bool empty, ret;
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empty = rxbuf.empty();
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ret = !empty;
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if (!empty) {
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rxbuf.read((char *)&c, 1);
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empty = rxbuf.empty();
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}
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DPRINTF(ConsoleVerbose, "in: \'%c\' %#02x more: %d, return: %d\n",
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isprint(c) ? c : ' ', c, !empty, ret);
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return ret;
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}
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uint64_t
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SimConsole::console_in()
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{
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uint8_t c;
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uint64_t value;
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if (in(c)) {
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value = RECEIVE_SUCCESS | c;
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if (!rxbuf.empty())
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value |= MORE_PENDING;
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} else {
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value = RECEIVE_NONE;
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}
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DPRINTF(ConsoleVerbose, "console_in: return: %#x\n", value);
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return value;
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}
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void
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SimConsole::out(char c)
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{
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#if TRACING_ON == 1
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if (DTRACE(Console)) {
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static char last = '\0';
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if (c != '\n' && c != '\r' ||
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last != '\n' && last != '\r') {
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if (c == '\n' || c == '\r') {
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int size = linebuf.size();
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char *buffer = new char[size + 1];
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linebuf.read(buffer, size);
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buffer[size] = '\0';
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DPRINTF(Console, "%s\n", buffer);
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delete [] buffer;
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} else {
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linebuf.write(c);
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}
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}
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last = c;
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}
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#endif
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txbuf.write(c);
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if (out_fd >= 0)
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write(c);
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if (outfile)
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outfile->write(&c, 1);
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DPRINTF(ConsoleVerbose, "out: \'%c\' %#02x\n",
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isprint(c) ? c : ' ', (int)c);
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}
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void
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SimConsole::serialize(ostream &os)
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{
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}
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void
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SimConsole::unserialize(Checkpoint *cp, const std::string §ion)
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{
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
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SimObjectParam<ConsoleListener *> listener;
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SimObjectParam<IntrControl *> intr_control;
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Param<string> output;
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Param<bool> append_name;
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Param<int> number;
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END_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
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BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
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INIT_PARAM(listener, "console listener"),
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INIT_PARAM(intr_control, "interrupt controller"),
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INIT_PARAM(output, "file to dump output to"),
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INIT_PARAM_DFLT(append_name, "append name() to filename", true),
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INIT_PARAM_DFLT(number, "console number", 0)
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END_INIT_SIM_OBJECT_PARAMS(SimConsole)
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CREATE_SIM_OBJECT(SimConsole)
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{
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string filename = output;
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ostream *stream = NULL;
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if (!filename.empty()) {
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if (append_name)
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filename += "." + getInstanceName();
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stream = simout.find(filename);
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}
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SimConsole *console = new SimConsole(getInstanceName(), stream, number);
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((ConsoleListener *)listener)->add(console);
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return console;
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}
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REGISTER_SIM_OBJECT("SimConsole", SimConsole)
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////////////////////////////////////////////////////////////////////////
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//
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//
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ConsoleListener::ConsoleListener(const string &name)
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: SimObject(name), event(NULL)
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{}
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ConsoleListener::~ConsoleListener()
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{
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if (event)
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delete event;
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}
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void
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ConsoleListener::Event::process(int revent)
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{
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listener->accept();
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}
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///////////////////////////////////////////////////////////////////////
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// socket creation and console attach
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//
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void
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ConsoleListener::listen(int port)
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{
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while (!listener.listen(port, true)) {
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DPRINTF(Console,
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": can't bind address console port %d inuse PID %d\n",
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port, getpid());
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port++;
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}
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ccprintf(cerr, "Listening for console connection on port %d\n", port);
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event = new Event(this, listener.getfd(), POLLIN);
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pollQueue.schedule(event);
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}
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void
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ConsoleListener::add(SimConsole *cons)
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{ ConsoleList.push_back(cons);}
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void
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ConsoleListener::accept()
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{
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if (!listener.islistening())
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panic("%s: cannot accept a connection if not listening!", name());
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int sfd = listener.accept(true);
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if (sfd != -1) {
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iter_t i = ConsoleList.begin();
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iter_t end = ConsoleList.end();
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if (i == end) {
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close(sfd);
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} else {
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(*i)->attach(sfd, this);
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i = ConsoleList.erase(i);
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}
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}
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(ConsoleListener)
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Param<int> port;
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END_DECLARE_SIM_OBJECT_PARAMS(ConsoleListener)
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BEGIN_INIT_SIM_OBJECT_PARAMS(ConsoleListener)
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INIT_PARAM_DFLT(port, "listen port", 3456)
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END_INIT_SIM_OBJECT_PARAMS(ConsoleListener)
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CREATE_SIM_OBJECT(ConsoleListener)
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{
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ConsoleListener *listener = new ConsoleListener(getInstanceName());
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listener->listen(port);
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return listener;
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}
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REGISTER_SIM_OBJECT("ConsoleListener", ConsoleListener)
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