Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
180 lines
6.9 KiB
C
180 lines
6.9 KiB
C
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Device register definitions for a device's PCI config space
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*/
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#ifndef __PCIREG_H__
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#define __PCIREG_H__
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#include <sys/types.h>
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union PCIConfig {
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uint8_t data[64];
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struct hdr {
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uint16_t vendor;
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uint16_t device;
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uint16_t command;
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uint16_t status;
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uint8_t revision;
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uint8_t progIF;
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uint8_t subClassCode;
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uint8_t classCode;
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uint8_t cacheLineSize;
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uint8_t latencyTimer;
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uint8_t headerType;
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uint8_t bist;
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union {
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struct {
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uint32_t baseAddr0;
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uint32_t baseAddr1;
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uint32_t baseAddr2;
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uint32_t baseAddr3;
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uint32_t baseAddr4;
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uint32_t baseAddr5;
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uint32_t cardbusCIS;
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uint16_t subsystemVendorID;
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uint16_t subsystemID;
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uint32_t expansionROM;
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uint32_t reserved0;
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uint32_t reserved1;
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uint8_t interruptLine;
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uint8_t interruptPin;
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uint8_t minimumGrant;
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uint8_t maximumLatency;
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} pci0;
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struct {
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uint32_t baseAddr0;
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uint32_t baseAddr1;
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uint8_t priBusNum;
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uint8_t secBusNum;
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uint8_t subBusNum;
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uint8_t secLatency;
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uint8_t ioBase;
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uint8_t minimumGrantioLimit;
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uint16_t secStatus;
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uint16_t memBase;
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uint16_t memLimit;
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uint16_t prefetchMemBase;
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uint16_t prefetchMemLimit;
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uint32_t prfBaseUpper32;
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uint32_t prfLimitUpper32;
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uint16_t ioBaseUpper16;
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uint16_t ioLimitUpper16;
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uint32_t reserved0;
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uint32_t expansionROM;
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uint8_t interruptLine;
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uint8_t interruptPin;
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uint16_t bridgeControl;
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} pci1;
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};
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} hdr;
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};
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// Common PCI offsets
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#define PCI_VENDOR_ID 0x00 // Vendor ID ro
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#define PCI_DEVICE_ID 0x02 // Device ID ro
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#define PCI_COMMAND 0x04 // Command rw
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#define PCI_STATUS 0x06 // Status rw
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#define PCI_REVISION_ID 0x08 // Revision ID ro
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#define PCI_CLASS_CODE 0x09 // Class Code ro
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#define PCI_SUB_CLASS_CODE 0x0A // Sub Class Code ro
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#define PCI_BASE_CLASS_CODE 0x0B // Base Class Code ro
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#define PCI_CACHE_LINE_SIZE 0x0C // Cache Line Size ro+
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#define PCI_LATENCY_TIMER 0x0D // Latency Timer ro+
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#define PCI_HEADER_TYPE 0x0E // Header Type ro
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#define PCI_BIST 0x0F // Built in self test rw
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// some pci command reg bitfields
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#define PCI_CMD_BME 0x04 // Bus master function enable
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#define PCI_CMD_MSE 0x02 // Memory Space Access enable
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#define PCI_CMD_IOSE 0x01 // I/O space enable
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// Type 0 PCI offsets
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#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
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#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw
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#define PCI0_BASE_ADDR2 0x18 // Base Address 2 rw
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#define PCI0_BASE_ADDR3 0x1C // Base Address 3 rw
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#define PCI0_BASE_ADDR4 0x20 // Base Address 4 rw
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#define PCI0_BASE_ADDR5 0x24 // Base Address 5 rw
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#define PCI0_CIS 0x28 // CardBus CIS Pointer ro
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#define PCI0_SUB_VENDOR_ID 0x2C // Sub-Vendor ID ro
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#define PCI0_SUB_SYSTEM_ID 0x2E // Sub-System ID ro
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#define PCI0_ROM_BASE_ADDR 0x30 // Expansion ROM Base Address rw
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#define PCI0_RESERVED0 0x34
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#define PCI0_RESERVED1 0x38
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#define PCI0_INTERRUPT_LINE 0x3C // Interrupt Line rw
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#define PCI0_INTERRUPT_PIN 0x3D // Interrupt Pin ro
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#define PCI0_MINIMUM_GRANT 0x3E // Maximum Grant ro
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#define PCI0_MAXIMUM_LATENCY 0x3F // Maximum Latency ro
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// Type 1 PCI offsets
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#define PCI1_BASE_ADDR0 0x10 // Base Address 0 rw
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#define PCI1_BASE_ADDR1 0x14 // Base Address 1 rw
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#define PCI1_PRI_BUS_NUM 0x18 // Primary Bus Number rw
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#define PCI1_SEC_BUS_NUM 0x19 // Secondary Bus Number rw
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#define PCI1_SUB_BUS_NUM 0x1A // Subordinate Bus Number rw
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#define PCI1_SEC_LAT_TIMER 0x1B // Secondary Latency Timer ro+
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#define PCI1_IO_BASE 0x1C // I/O Base rw
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#define PCI1_IO_LIMIT 0x1D // I/O Limit rw
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#define PCI1_SECONDARY_STATUS 0x1E // Secondary Status rw
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#define PCI1_MEM_BASE 0x20 // Memory Base rw
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#define PCI1_MEM_LIMIT 0x22 // Memory Limit rw
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#define PCI1_PRF_MEM_BASE 0x24 // Prefetchable Memory Base rw
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#define PCI1_PRF_MEM_LIMIT 0x26 // Prefetchable Memory Limit rw
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#define PCI1_PRF_BASE_UPPER 0x28 // Prefetchable Base Upper 32 rw
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#define PCI1_PRF_LIMIT_UPPER 0x2C // Prefetchable Limit Upper 32 rw
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#define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw
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#define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw
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#define PCI1_RESERVED 0x34 // Reserved ro
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#define PCI1_ROM_BASE_ADDR 0x38 // Expansion ROM Base Address rw
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#define PCI1_INTR_LINE 0x3C // Interrupt Line rw
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#define PCI1_INTR_PIN 0x3D // Interrupt Pin ro
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#define PCI1_BRIDGE_CTRL 0x3E // Bridge Control rw
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// Device specific offsets
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#define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes
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// Some Vendor IDs
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#define PCI_VENDOR_DEC 0x1011
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#define PCI_VENDOR_NCR 0x101A
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#define PCI_VENDOR_QLOGIC 0x1077
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#define PCI_VENDOR_SIMOS 0x1291
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// Some Product IDs
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#define PCI_PRODUCT_DEC_PZA 0x0008
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#define PCI_PRODUCT_NCR_810 0x0001
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#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
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#define PCI_PRODUCT_SIMOS_SIMOS 0x1291
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#define PCI_PRODUCT_SIMOS_ETHER 0x1292
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#endif // __PCIREG_H__
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