10c79efe55
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
636 lines
18 KiB
C++
636 lines
18 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_CPU_REGFILE_HH__
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#define __CPU_O3_CPU_REGFILE_HH__
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// @todo: Destructor
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/faults.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/o3/comm.hh"
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#if FULL_SYSTEM
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#include "arch/alpha/ev5.hh"
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#include "kern/kernel_stats.hh"
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using namespace EV5;
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#endif
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// This really only depends on the ISA, and not the Impl. It might be nicer
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// to see if I can make it depend on nothing...
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// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
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// and should go in the AlphaFullCPU.
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template <class Impl>
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class PhysRegFile
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{
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//Note that most of the definitions of the IntReg, FloatReg, etc. exist
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//within the Impl/ISA class and not within this PhysRegFile class.
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//Will need some way to allow stuff like swap_palshadow to access the
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//correct registers. Might require code changes to swap_palshadow and
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//other execution contexts.
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//Will make these registers public for now, but they probably should
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//be private eventually with some accessor functions.
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public:
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typedef typename Impl::ISA ISA;
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typedef typename Impl::FullCPU FullCPU;
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PhysRegFile(unsigned _numPhysicalIntRegs,
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unsigned _numPhysicalFloatRegs);
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//Everything below should be pretty well identical to the normal
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//register file that exists within AlphaISA class.
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//The duplication is unfortunate but it's better than having
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//different ways to access certain registers.
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//Add these in later when everything else is in place
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// void serialize(std::ostream &os);
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// void unserialize(Checkpoint *cp, const std::string §ion);
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uint64_t readIntReg(PhysRegIndex reg_idx)
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{
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assert(reg_idx < numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to int register %i, has data "
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"%i\n", int(reg_idx), intRegFile[reg_idx]);
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return intRegFile[reg_idx];
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}
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float readFloatRegSingle(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to float register %i as single, has "
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"data %8.8f\n", int(reg_idx), (float)floatRegFile[reg_idx].d);
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return (float)floatRegFile[reg_idx].d;
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}
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double readFloatRegDouble(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to float register %i as double, has "
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" data %8.8f\n", int(reg_idx), floatRegFile[reg_idx].d);
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return floatRegFile[reg_idx].d;
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}
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uint64_t readFloatRegInt(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to float register %i as int, has data "
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"%lli\n", int(reg_idx), floatRegFile[reg_idx].q);
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return floatRegFile[reg_idx].q;
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}
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void setIntReg(PhysRegIndex reg_idx, uint64_t val)
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{
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assert(reg_idx < numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n",
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int(reg_idx), val);
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intRegFile[reg_idx] = val;
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}
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void setFloatRegSingle(PhysRegIndex reg_idx, float val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
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int(reg_idx), val);
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floatRegFile[reg_idx].d = (double)val;
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}
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void setFloatRegDouble(PhysRegIndex reg_idx, double val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
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int(reg_idx), val);
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floatRegFile[reg_idx].d = val;
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}
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void setFloatRegInt(PhysRegIndex reg_idx, uint64_t val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
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int(reg_idx), val);
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floatRegFile[reg_idx].q = val;
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}
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uint64_t readPC()
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{
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return pc;
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}
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void setPC(uint64_t val)
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{
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pc = val;
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}
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void setNextPC(uint64_t val)
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{
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npc = val;
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}
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//Consider leaving this stuff and below in some implementation specific
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//file as opposed to the general register file. Or have a derived class.
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uint64_t readUniq()
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{
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return miscRegs.uniq;
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}
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void setUniq(uint64_t val)
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{
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miscRegs.uniq = val;
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}
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uint64_t readFpcr()
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{
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return miscRegs.fpcr;
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}
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void setFpcr(uint64_t val)
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{
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miscRegs.fpcr = val;
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}
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#if FULL_SYSTEM
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uint64_t readIpr(int idx, Fault * &fault);
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Fault * setIpr(int idx, uint64_t val);
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InternalProcReg *getIpr() { return ipr; }
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int readIntrFlag() { return intrflag; }
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void setIntrFlag(int val) { intrflag = val; }
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#endif
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// These should be private eventually, but will be public for now
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// so that I can hack around the initregs issue.
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public:
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/** (signed) integer register file. */
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IntReg *intRegFile;
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/** Floating point register file. */
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FloatReg *floatRegFile;
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/** Miscellaneous register file. */
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MiscRegFile miscRegs;
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/** Program counter. */
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Addr pc;
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/** Next-cycle program counter. */
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Addr npc;
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#if FULL_SYSTEM
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private:
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// This is ISA specifc stuff; remove it eventually once ISAImpl is used
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IntReg palregs[NumIntRegs]; // PAL shadow registers
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InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
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int intrflag; // interrupt flag
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bool pal_shadow; // using pal_shadow registers
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#endif
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private:
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FullCPU *cpu;
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public:
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void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; }
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unsigned numPhysicalIntRegs;
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unsigned numPhysicalFloatRegs;
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};
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template <class Impl>
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PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
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unsigned _numPhysicalFloatRegs)
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: numPhysicalIntRegs(_numPhysicalIntRegs),
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numPhysicalFloatRegs(_numPhysicalFloatRegs)
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{
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intRegFile = new IntReg[numPhysicalIntRegs];
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floatRegFile = new FloatReg[numPhysicalFloatRegs];
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memset(intRegFile, 0, sizeof(*intRegFile));
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memset(floatRegFile, 0, sizeof(*floatRegFile));
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}
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#if FULL_SYSTEM
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//Problem: This code doesn't make sense at the RegFile level because it
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//needs things such as the itb and dtb. Either put it at the CPU level or
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//the DynInst level.
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template <class Impl>
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uint64_t
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PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
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{
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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case ISA::IPR_PALtemp0:
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case ISA::IPR_PALtemp1:
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case ISA::IPR_PALtemp2:
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case ISA::IPR_PALtemp3:
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case ISA::IPR_PALtemp4:
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case ISA::IPR_PALtemp5:
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case ISA::IPR_PALtemp6:
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case ISA::IPR_PALtemp7:
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case ISA::IPR_PALtemp8:
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case ISA::IPR_PALtemp9:
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case ISA::IPR_PALtemp10:
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case ISA::IPR_PALtemp11:
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case ISA::IPR_PALtemp12:
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case ISA::IPR_PALtemp13:
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case ISA::IPR_PALtemp14:
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case ISA::IPR_PALtemp15:
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case ISA::IPR_PALtemp16:
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case ISA::IPR_PALtemp17:
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case ISA::IPR_PALtemp18:
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case ISA::IPR_PALtemp19:
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case ISA::IPR_PALtemp20:
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case ISA::IPR_PALtemp21:
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case ISA::IPR_PALtemp22:
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case ISA::IPR_PALtemp23:
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case ISA::IPR_PAL_BASE:
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case ISA::IPR_IVPTBR:
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case ISA::IPR_DC_MODE:
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case ISA::IPR_MAF_MODE:
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case ISA::IPR_ISR:
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case ISA::IPR_EXC_ADDR:
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case ISA::IPR_IC_PERR_STAT:
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case ISA::IPR_DC_PERR_STAT:
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case ISA::IPR_MCSR:
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case ISA::IPR_ASTRR:
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case ISA::IPR_ASTER:
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case ISA::IPR_SIRR:
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case ISA::IPR_ICSR:
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case ISA::IPR_ICM:
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case ISA::IPR_DTB_CM:
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case ISA::IPR_IPLR:
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case ISA::IPR_INTID:
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case ISA::IPR_PMCTR:
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// no side-effect
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retval = ipr[idx];
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break;
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case ISA::IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= curTick & ULL(0x00000000ffffffff);
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break;
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case ISA::IPR_VA:
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retval = ipr[idx];
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break;
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case ISA::IPR_VA_FORM:
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case ISA::IPR_MM_STAT:
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case ISA::IPR_IFAULT_VA_FORM:
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case ISA::IPR_EXC_MASK:
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case ISA::IPR_EXC_SUM:
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retval = ipr[idx];
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break;
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case ISA::IPR_DTB_PTE:
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{
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typename ISA::PTE &pte = cpu->dtb->index(1);
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
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}
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break;
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// write only registers
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case ISA::IPR_HWINT_CLR:
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case ISA::IPR_SL_XMIT:
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case ISA::IPR_DC_FLUSH:
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case ISA::IPR_IC_FLUSH:
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case ISA::IPR_ALT_MODE:
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case ISA::IPR_DTB_IA:
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case ISA::IPR_DTB_IAP:
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case ISA::IPR_ITB_IA:
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case ISA::IPR_ITB_IAP:
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fault = UnimplementedOpcodeFault;
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break;
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default:
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// invalid IPR
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fault = UnimplementedOpcodeFault;
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break;
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}
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return retval;
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}
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extern int break_ipl;
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template <class Impl>
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Fault *
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PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
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{
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uint64_t old;
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switch (idx) {
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case ISA::IPR_PALtemp0:
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case ISA::IPR_PALtemp1:
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case ISA::IPR_PALtemp2:
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case ISA::IPR_PALtemp3:
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case ISA::IPR_PALtemp4:
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case ISA::IPR_PALtemp5:
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case ISA::IPR_PALtemp6:
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case ISA::IPR_PALtemp7:
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case ISA::IPR_PALtemp8:
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case ISA::IPR_PALtemp9:
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case ISA::IPR_PALtemp10:
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case ISA::IPR_PALtemp11:
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case ISA::IPR_PALtemp12:
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case ISA::IPR_PALtemp13:
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case ISA::IPR_PALtemp14:
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case ISA::IPR_PALtemp15:
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case ISA::IPR_PALtemp16:
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case ISA::IPR_PALtemp17:
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case ISA::IPR_PALtemp18:
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case ISA::IPR_PALtemp19:
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case ISA::IPR_PALtemp20:
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case ISA::IPR_PALtemp21:
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case ISA::IPR_PALtemp22:
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case ISA::IPR_PAL_BASE:
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case ISA::IPR_IC_PERR_STAT:
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case ISA::IPR_DC_PERR_STAT:
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case ISA::IPR_PMCTR:
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// write entire quad w/ no side-effect
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ipr[idx] = val;
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break;
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case ISA::IPR_CC_CTL:
|
|
// This IPR resets the cycle counter. We assume this only
|
|
// happens once... let's verify that.
|
|
assert(ipr[idx] == 0);
|
|
ipr[idx] = 1;
|
|
break;
|
|
|
|
case ISA::IPR_CC:
|
|
// This IPR only writes the upper 64 bits. It's ok to write
|
|
// all 64 here since we mask out the lower 32 in rpcc (see
|
|
// isa_desc).
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case ISA::IPR_PALtemp23:
|
|
// write entire quad w/ no side-effect
|
|
old = ipr[idx];
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case ISA::IPR_DTB_PTE:
|
|
// write entire quad w/ no side-effect, tag is forthcoming
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case ISA::IPR_EXC_ADDR:
|
|
// second least significant bit in PC is always zero
|
|
ipr[idx] = val & ~2;
|
|
break;
|
|
|
|
case ISA::IPR_ASTRR:
|
|
case ISA::IPR_ASTER:
|
|
// only write least significant four bits - privilege mask
|
|
ipr[idx] = val & 0xf;
|
|
break;
|
|
|
|
case ISA::IPR_IPLR:
|
|
// only write least significant five bits - interrupt level
|
|
ipr[idx] = val & 0x1f;
|
|
break;
|
|
|
|
case ISA::IPR_DTB_CM:
|
|
|
|
case ISA::IPR_ICM:
|
|
// only write two mode bits - processor mode
|
|
ipr[idx] = val & 0x18;
|
|
break;
|
|
|
|
case ISA::IPR_ALT_MODE:
|
|
// only write two mode bits - processor mode
|
|
ipr[idx] = val & 0x18;
|
|
break;
|
|
|
|
case ISA::IPR_MCSR:
|
|
// more here after optimization...
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case ISA::IPR_SIRR:
|
|
// only write software interrupt mask
|
|
ipr[idx] = val & 0x7fff0;
|
|
break;
|
|
|
|
case ISA::IPR_ICSR:
|
|
ipr[idx] = val & ULL(0xffffff0300);
|
|
break;
|
|
|
|
case ISA::IPR_IVPTBR:
|
|
case ISA::IPR_MVPTBR:
|
|
ipr[idx] = val & ULL(0xffffffffc0000000);
|
|
break;
|
|
|
|
case ISA::IPR_DC_TEST_CTL:
|
|
ipr[idx] = val & 0x1ffb;
|
|
break;
|
|
|
|
case ISA::IPR_DC_MODE:
|
|
case ISA::IPR_MAF_MODE:
|
|
ipr[idx] = val & 0x3f;
|
|
break;
|
|
|
|
case ISA::IPR_ITB_ASN:
|
|
ipr[idx] = val & 0x7f0;
|
|
break;
|
|
|
|
case ISA::IPR_DTB_ASN:
|
|
ipr[idx] = val & ULL(0xfe00000000000000);
|
|
break;
|
|
|
|
case ISA::IPR_EXC_SUM:
|
|
case ISA::IPR_EXC_MASK:
|
|
// any write to this register clears it
|
|
ipr[idx] = 0;
|
|
break;
|
|
|
|
case ISA::IPR_INTID:
|
|
case ISA::IPR_SL_RCV:
|
|
case ISA::IPR_MM_STAT:
|
|
case ISA::IPR_ITB_PTE_TEMP:
|
|
case ISA::IPR_DTB_PTE_TEMP:
|
|
// read-only registers
|
|
return UnimplementedOpcodeFault;
|
|
|
|
case ISA::IPR_HWINT_CLR:
|
|
case ISA::IPR_SL_XMIT:
|
|
case ISA::IPR_DC_FLUSH:
|
|
case ISA::IPR_IC_FLUSH:
|
|
// the following are write only
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case ISA::IPR_DTB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
cpu->dtb->flushAll();
|
|
break;
|
|
|
|
case ISA::IPR_DTB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
cpu->dtb->flushProcesses();
|
|
break;
|
|
|
|
case ISA::IPR_DTB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]));
|
|
break;
|
|
|
|
case ISA::IPR_DTB_TAG: {
|
|
struct ISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
cpu->dtb->insert(val, pte);
|
|
}
|
|
break;
|
|
|
|
case ISA::IPR_ITB_PTE: {
|
|
struct ISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (ITB_PTE_GH(val) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = ITB_PTE_PPN(val);
|
|
pte.xre = ITB_PTE_XRE(val);
|
|
pte.xwe = 0;
|
|
pte.fonr = ITB_PTE_FONR(val);
|
|
pte.fonw = ITB_PTE_FONW(val);
|
|
pte.asma = ITB_PTE_ASMA(val);
|
|
pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte);
|
|
}
|
|
break;
|
|
|
|
case ISA::IPR_ITB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
cpu->itb->flushAll();
|
|
break;
|
|
|
|
case ISA::IPR_ITB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
cpu->itb->flushProcesses();
|
|
break;
|
|
|
|
case ISA::IPR_ITB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]));
|
|
break;
|
|
|
|
default:
|
|
// invalid IPR
|
|
return UnimplementedOpcodeFault;
|
|
}
|
|
|
|
// no error...
|
|
return NoFault;
|
|
}
|
|
|
|
#endif // #if FULL_SYSTEM
|
|
|
|
#endif // __CPU_O3_CPU_REGFILE_HH__
|