Ron Dreslinski ea11c7bdbe Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory ... configs/test/test.py: Update to use new cpu getPort functionality src/cpu/base.cc: Make cpu's a memObject to expose getPort interface src/cpu/base.hh: Make cpu's a memObject to export getPort interface src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Now use the connector via getPort interface src/mem/cache/base_cache.cc: Make sure the cache recognizes all port names --HG-- extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61		2006-07-07 15:15:11 -04:00
..
fs.py	Add default responder to bus	2006-07-06 14:41:01 -04:00
hello	Compiles now (with CPU_MODELS=SimpleCPU), but hangs	2006-03-10 10:01:29 -05:00
hello_mips	Minor changes for FP ... MIPS now works for floating-point programs...	2006-05-07 14:09:19 -04:00
hello_sparc	Changed the hello_sparc executable back to the cross compiled one	2006-04-28 13:11:32 -04:00
SysPaths.py	minor device fixups	2006-06-18 11:10:08 -04:00
test.py	Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory	2006-07-07 15:15:11 -04:00