373 lines
13 KiB
C++
373 lines
13 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Korey Sewell
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////////////////////////////////////////////////////////////////////
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//
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// Floating Point operate instructions
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//
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output header {{
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/**
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* Base class for FP operations.
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*/
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class FPOp : public MipsStaticInst
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{
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protected:
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/// Constructor
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FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
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{
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}
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//std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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//needs function to check for fpEnable or not
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};
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class FPCompareOp : public FPOp
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{
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protected:
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FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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ccprintf(ss,"%d",CC);
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if(_numSrcRegs > 0) {
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ss << ", ";
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printReg(ss, _srcRegIdx[0]);
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}
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if(_numSrcRegs > 1) {
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ss << ", ";
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printReg(ss, _srcRegIdx[1]);
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}
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return ss.str();
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}
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}};
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output exec {{
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//If any operand is Nan return the appropriate QNaN
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template <class T>
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bool
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fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
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Trace::InstRecord *traceData)
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{
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uint64_t mips_nan = 0;
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T src_op = 0;
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int size = sizeof(src_op) * 8;
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for (int i = 0; i < inst->numSrcRegs(); i++) {
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uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
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if (isNan(&src_bits, size) ) {
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if (isSnan(&src_bits, size)) {
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switch (size)
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{
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case 32: mips_nan = MIPS32_QNAN; break;
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case 64: mips_nan = MIPS64_QNAN; break;
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default: panic("Unsupported Floating Point Size (%d)", size);
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}
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} else {
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mips_nan = src_bits;
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}
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xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
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if (traceData) { traceData->setData(mips_nan); }
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return true;
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}
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}
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return false;
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}
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template <class T>
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bool
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fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
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Trace::InstRecord *traceData)
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{
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uint64_t mips_nan = 0;
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T src_op = dest_val;
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int size = sizeof(src_op) * 8;
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if (isNan(&src_op, size)) {
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switch (size)
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{
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case 32: mips_nan = MIPS32_QNAN; break;
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case 64: mips_nan = MIPS64_QNAN; break;
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default: panic("Unsupported Floating Point Size (%d)", size);
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}
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//Set value to QNAN
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cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
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//Read FCSR from FloatRegFile
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uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
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//Write FCSR from FloatRegFile
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cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
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if (traceData) { traceData->setData(mips_nan); }
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return true;
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}
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return false;
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}
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void
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fpResetCauseBits(%(CPU_exec_context)s *cpu)
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{
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//Read FCSR from FloatRegFile
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uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
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fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
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//Write FCSR from FloatRegFile
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cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
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}
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}};
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def template FloatingPointExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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//When is the right time to reset cause bits?
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//start of every instruction or every cycle?
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#if FULL_SYSTEM
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fpResetCauseBits(xc);
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#endif
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%(op_decl)s;
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%(op_rd)s;
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//Check if any FP operand is a NaN value
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if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
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%(code)s;
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//Change this code for Full-System/Sycall Emulation
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//separation
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//----
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//Should Full System-Mode throw a fault here?
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//----
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//Check for IEEE 754 FP Exceptions
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//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
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if (
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#if FULL_SYSTEM
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!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
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#endif
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fault == NoFault)
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{
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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// Primary format for float point operate instructions:
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def format FloatOp(code, *flags) {{
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iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = FloatingPointExecute.subst(iop)
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}};
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def format FloatCompareOp(cond_code, *flags) {{
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import sys
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code = 'bool cond;\n'
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if '.sf' in cond_code or 'SinglePrecision' in flags:
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if 'QnanException' in flags:
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code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
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code += '\tFCSR = genInvalidVector(FCSR);\n'
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code += '\treturn NoFault;'
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code += '}\n else '
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code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
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elif '.df' in cond_code or 'DoublePrecision' in flags:
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if 'QnanException' in flags:
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code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
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code += '\tFCSR = genInvalidVector(FCSR);\n'
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code += '\treturn NoFault;'
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code += '}\n else '
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code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
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else:
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sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
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if 'UnorderedTrue' in flags:
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code += 'cond = 1;\n'
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elif 'UnorderedFalse' in flags:
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code += 'cond = 0;\n'
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else:
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sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
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code += '} else {\n'
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code += cond_code + '}'
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code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
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iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format FloatConvertOp(code, *flags) {{
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import sys
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#Determine Source Type
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convert = 'fpConvert('
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if '.sf' in code:
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code = 'float ' + code + '\n'
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convert += 'SINGLE_TO_'
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elif '.df' in code:
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code = 'double ' + code + '\n'
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convert += 'DOUBLE_TO_'
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elif '.uw' in code:
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code = 'uint32_t ' + code + '\n'
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convert += 'WORD_TO_'
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elif '.ud' in code:
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code = 'uint64_t ' + code + '\n'
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convert += 'LONG_TO_'
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else:
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sys.exit("Error Determining Source Type for Conversion")
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#Determine Destination Type
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if 'ToSingle' in flags:
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code += 'Fd.uw = ' + convert + 'SINGLE, '
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elif 'ToDouble' in flags:
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code += 'Fd.ud = ' + convert + 'DOUBLE, '
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elif 'ToWord' in flags:
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code += 'Fd.uw = ' + convert + 'WORD, '
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elif 'ToLong' in flags:
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code += 'Fd.ud = ' + convert + 'LONG, '
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else:
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sys.exit("Error Determining Destination Type for Conversion")
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#Figure out how to round value
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if 'Ceil' in flags:
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code += 'ceil(val)); '
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elif 'Floor' in flags:
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code += 'floor(val)); '
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elif 'Round' in flags:
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code += 'roundFP(val, 0)); '
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elif 'Trunc' in flags:
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code += 'truncFP(val));'
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else:
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code += 'val); '
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iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format FloatAccOp(code, *flags) {{
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iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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// Primary format for float64 operate instructions:
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def format Float64Op(code, *flags) {{
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iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
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import sys
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code = 'bool cond1, cond2;\n'
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code += 'bool code_block1, code_block2;\n'
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code += 'code_block1 = code_block2 = true;\n'
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if 'QnanException' in flags:
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code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
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code += '\tFCSR = genInvalidVector(FCSR);\n'
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code += 'code_block1 = false;'
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code += '}\n'
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code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
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code += '\tFCSR = genInvalidVector(FCSR);\n'
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code += 'code_block2 = false;'
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code += '}\n'
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code += 'if (code_block1) {'
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code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
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if 'UnorderedTrue' in flags:
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code += 'cond1 = 1;\n'
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elif 'UnorderedFalse' in flags:
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code += 'cond1 = 0;\n'
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else:
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sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
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code += '} else {\n'
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code += cond_code1
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code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
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code += 'if (code_block2) {'
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code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
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if 'UnorderedTrue' in flags:
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code += 'cond2 = 1;\n'
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elif 'UnorderedFalse' in flags:
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code += 'cond2 = 0;\n'
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else:
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sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
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code += '} else {\n'
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code += cond_code2
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code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
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iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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