225 lines
3.8 KiB
INI
225 lines
3.8 KiB
INI
[root]
|
|
type=Root
|
|
children=system
|
|
checkpoint=
|
|
clock=1000000000000
|
|
max_tick=0
|
|
output_file=cout
|
|
progress_interval=0
|
|
|
|
[debug]
|
|
break_cycles=
|
|
|
|
[exetrace]
|
|
intel_format=false
|
|
pc_symbol=true
|
|
print_cpseq=false
|
|
print_cycle=true
|
|
print_data=true
|
|
print_effaddr=true
|
|
print_fetchseq=false
|
|
print_iregs=false
|
|
print_opclass=true
|
|
print_thread=true
|
|
speculative=true
|
|
trace_system=client
|
|
|
|
[serialize]
|
|
count=10
|
|
cycle=0
|
|
dir=cpt.%012d
|
|
period=0
|
|
|
|
[stats]
|
|
descriptions=true
|
|
dump_cycle=0
|
|
dump_period=0
|
|
dump_reset=false
|
|
ignore_events=
|
|
mysql_db=
|
|
mysql_host=
|
|
mysql_password=
|
|
mysql_user=
|
|
project_name=test
|
|
simulation_name=test
|
|
simulation_sample=0
|
|
text_compat=true
|
|
text_file=m5stats.txt
|
|
|
|
[system]
|
|
type=System
|
|
children=cpu membus physmem
|
|
mem_mode=atomic
|
|
physmem=system.physmem
|
|
|
|
[system.cpu]
|
|
type=TimingSimpleCPU
|
|
children=dcache icache l2cache toL2Bus workload
|
|
clock=1
|
|
defer_registration=false
|
|
function_trace=false
|
|
function_trace_start=0
|
|
max_insts_all_threads=0
|
|
max_insts_any_thread=0
|
|
max_loads_all_threads=0
|
|
max_loads_any_thread=0
|
|
mem=system.cpu.dcache
|
|
system=system
|
|
workload=system.cpu.workload
|
|
dcache_port=system.cpu.dcache.cpu_side
|
|
icache_port=system.cpu.icache.cpu_side
|
|
|
|
[system.cpu.dcache]
|
|
type=BaseCache
|
|
adaptive_compression=false
|
|
assoc=2
|
|
block_size=64
|
|
compressed_bus=false
|
|
compression_latency=0
|
|
do_copy=false
|
|
hash_delay=1
|
|
hit_latency=1
|
|
latency=1
|
|
lifo=false
|
|
max_miss_count=0
|
|
mshrs=10
|
|
prefetch_access=false
|
|
prefetch_cache_check_push=true
|
|
prefetch_data_accesses_only=false
|
|
prefetch_degree=1
|
|
prefetch_latency=10
|
|
prefetch_miss=false
|
|
prefetch_past_page=false
|
|
prefetch_policy=none
|
|
prefetch_serial_squash=false
|
|
prefetch_use_cpu_id=true
|
|
prefetcher_size=100
|
|
prioritizeRequests=false
|
|
protocol=Null
|
|
repl=Null
|
|
size=262144
|
|
split=false
|
|
split_size=0
|
|
store_compressed=false
|
|
subblock_size=0
|
|
tgts_per_mshr=5
|
|
trace_addr=0
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.dcache_port
|
|
mem_side=system.cpu.toL2Bus.port[1]
|
|
|
|
[system.cpu.icache]
|
|
type=BaseCache
|
|
adaptive_compression=false
|
|
assoc=2
|
|
block_size=64
|
|
compressed_bus=false
|
|
compression_latency=0
|
|
do_copy=false
|
|
hash_delay=1
|
|
hit_latency=1
|
|
latency=1
|
|
lifo=false
|
|
max_miss_count=0
|
|
mshrs=10
|
|
prefetch_access=false
|
|
prefetch_cache_check_push=true
|
|
prefetch_data_accesses_only=false
|
|
prefetch_degree=1
|
|
prefetch_latency=10
|
|
prefetch_miss=false
|
|
prefetch_past_page=false
|
|
prefetch_policy=none
|
|
prefetch_serial_squash=false
|
|
prefetch_use_cpu_id=true
|
|
prefetcher_size=100
|
|
prioritizeRequests=false
|
|
protocol=Null
|
|
repl=Null
|
|
size=131072
|
|
split=false
|
|
split_size=0
|
|
store_compressed=false
|
|
subblock_size=0
|
|
tgts_per_mshr=5
|
|
trace_addr=0
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.icache_port
|
|
mem_side=system.cpu.toL2Bus.port[0]
|
|
|
|
[system.cpu.l2cache]
|
|
type=BaseCache
|
|
adaptive_compression=false
|
|
assoc=2
|
|
block_size=64
|
|
compressed_bus=false
|
|
compression_latency=0
|
|
do_copy=false
|
|
hash_delay=1
|
|
hit_latency=1
|
|
latency=1
|
|
lifo=false
|
|
max_miss_count=0
|
|
mshrs=10
|
|
prefetch_access=false
|
|
prefetch_cache_check_push=true
|
|
prefetch_data_accesses_only=false
|
|
prefetch_degree=1
|
|
prefetch_latency=10
|
|
prefetch_miss=false
|
|
prefetch_past_page=false
|
|
prefetch_policy=none
|
|
prefetch_serial_squash=false
|
|
prefetch_use_cpu_id=true
|
|
prefetcher_size=100
|
|
prioritizeRequests=false
|
|
protocol=Null
|
|
repl=Null
|
|
size=2097152
|
|
split=false
|
|
split_size=0
|
|
store_compressed=false
|
|
subblock_size=0
|
|
tgts_per_mshr=5
|
|
trace_addr=0
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.toL2Bus.port[2]
|
|
mem_side=system.membus.port[1]
|
|
|
|
[system.cpu.toL2Bus]
|
|
type=Bus
|
|
bus_id=0
|
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
|
|
|
[system.cpu.workload]
|
|
type=LiveProcess
|
|
cmd=hello
|
|
env=
|
|
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
|
input=cin
|
|
output=cout
|
|
system=system
|
|
|
|
[system.membus]
|
|
type=Bus
|
|
bus_id=0
|
|
port=system.physmem.port system.cpu.l2cache.mem_side
|
|
|
|
[system.physmem]
|
|
type=PhysicalMemory
|
|
file=
|
|
latency=1
|
|
range=0:134217727
|
|
port=system.membus.port[0]
|
|
|
|
[trace]
|
|
bufsize=0
|
|
dump_on_exit=false
|
|
file=cout
|
|
flags=
|
|
ignore=
|
|
start=0
|
|
|