cpu/base_dyn_inst.hh: Code cleanup --HG-- extra : convert_revision : 501c03f8e4346ffbcb545ddeee30c1f8ded9baa7
231 lines
7.2 KiB
C++
231 lines
7.2 KiB
C++
/*
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* Copyright (c) 2005-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_OZONE_DYN_INST_HH__
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#define __CPU_OZONE_DYN_INST_HH__
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#include "arch/isa_traits.hh"
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#include "config/full_system.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/ozone/cpu.hh" // MUST include this
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#include "cpu/inst_seq.hh"
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#include "cpu/ozone/simple_impl.hh" // Would be nice to not have to include this
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#include "cpu/ozone/ozone_impl.hh"
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#include <list>
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#include <vector>
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template <class Impl>
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class OzoneDynInst : public BaseDynInst<Impl>
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{
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public:
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// Typedefs
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typedef typename Impl::FullCPU FullCPU;
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typedef typename FullCPU::ImplState ImplState;
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// Typedef for DynInstPtr. This is really just a RefCountingPtr<OoODynInst>.
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef TheISA::ExtMachInst ExtMachInst;
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscReg MiscReg;
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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// Note that this is duplicated from the BaseDynInst class; I'm
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// simply not sure the enum would carry through so I could use it
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// in array declarations in this class.
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enum {
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MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
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MaxInstDestRegs = TheISA::MaxInstDestRegs
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};
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OzoneDynInst(FullCPU *cpu);
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OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
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InstSeqNum seq_num, FullCPU *cpu);
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OzoneDynInst(StaticInstPtr inst);
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~OzoneDynInst();
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void setSrcInst(DynInstPtr &newSrcInst, int regIdx)
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{ srcInsts[regIdx] = newSrcInst; }
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bool srcInstReady(int regIdx);
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void setPrevDestInst(DynInstPtr &oldDestInst, int regIdx)
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{ prevDestInst[regIdx] = oldDestInst; }
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DynInstPtr &getPrevDestInst(int regIdx)
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{ return prevDestInst[regIdx]; }
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void addDependent(DynInstPtr &dependent_inst);
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std::vector<DynInstPtr> &getDependents() { return dependents; }
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std::vector<DynInstPtr> &getMemDeps() { return memDependents; }
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std::list<DynInstPtr> &getMemSrcs() { return srcMemInsts; }
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void wakeDependents();
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void wakeMemDependents();
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void addMemDependent(DynInstPtr &inst) { memDependents.push_back(inst); }
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void addSrcMemInst(DynInstPtr &inst) { srcMemInsts.push_back(inst); }
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void markMemInstReady(OzoneDynInst<Impl> *inst);
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// For now I will remove instructions from the list when they wake
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// up. In the future, you only really need a counter.
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bool memDepReady() { return srcMemInsts.empty(); }
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private:
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void initInstPtrs();
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std::vector<DynInstPtr> dependents;
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std::vector<DynInstPtr> memDependents;
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std::list<DynInstPtr> srcMemInsts;
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/** The instruction that produces the value of the source
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* registers. These may be NULL if the value has already been
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* read from the source instruction.
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*/
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DynInstPtr srcInsts[MaxInstSrcRegs];
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/**
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* Previous rename instruction for this destination.
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*/
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DynInstPtr prevDestInst[MaxInstSrcRegs];
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public:
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Fault initiateAcc();
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Fault completeAcc();
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to redice overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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uint64_t readIntReg(const StaticInst *si, int idx)
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{
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return srcInsts[idx]->readIntResult();
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}
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float readFloatRegSingle(const StaticInst *si, int idx)
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{
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return srcInsts[idx]->readFloatResult();
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}
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double readFloatRegDouble(const StaticInst *si, int idx)
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{
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return srcInsts[idx]->readDoubleResult();
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}
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uint64_t readFloatRegInt(const StaticInst *si, int idx)
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{
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return srcInsts[idx]->readIntResult();
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}
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/** @todo: Make results into arrays so they can handle multiple dest
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* registers.
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*/
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void setIntReg(const StaticInst *si, int idx, uint64_t val)
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{
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BaseDynInst<Impl>::setIntReg(si, idx, val);
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}
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void setFloatRegSingle(const StaticInst *si, int idx, float val)
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{
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BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
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}
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void setFloatRegDouble(const StaticInst *si, int idx, double val)
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{
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BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
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}
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void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
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{
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BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
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}
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void setIntResult(uint64_t result) { this->instResult.integer = result; }
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void setDoubleResult(double result) { this->instResult.dbl = result; }
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bool srcsReady();
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bool eaSrcsReady();
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Fault execute();
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Fault executeEAComp()
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{ return NoFault; }
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Fault executeMemAcc()
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{ return this->staticInst->memAccInst()->execute(this, this->traceData); }
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void clearDependents();
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void clearMemDependents();
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public:
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// ISA stuff
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MiscReg readMiscReg(int misc_reg);
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MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
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Fault setMiscReg(int misc_reg, const MiscReg &val);
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Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
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#if FULL_SYSTEM
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Fault hwrei();
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int readIntrFlag();
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void setIntrFlag(int val);
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bool inPalMode();
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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#else
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void syscall();
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#endif
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ListIt iqIt;
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bool iqItValid;
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};
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#endif // __CPU_OZONE_DYN_INST_HH__
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