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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
Nilay Vaish 5abbb84f02 stats: updates due to branch predictor warming
2014-02-16 11:40:34 -06:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.842697 # Number of seconds simulated
sim_ticks 1842697218000 # Number of ticks simulated
final_tick 1842697218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 281851 # Simulator instruction rate (inst/s)
host_op_rate 281851 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7098045398 # Simulator tick rate (ticks/s)
host_mem_usage 310872 # Number of bytes of host memory used
host_seconds 259.61 # Real time elapsed on the host
sim_insts 73170192 # Number of instructions simulated
sim_ops 73170192 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 489152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 20102912 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 144448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2236224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 284928 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2526528 # Number of bytes read from this memory
system.physmem.bytes_read::total 28436544 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 489152 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 144448 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 284928 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 918528 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7459712 # Number of bytes written to this memory
system.physmem.bytes_written::total 7459712 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 7643 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 314108 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2257 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 34941 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 4452 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 39477 # Number of read requests responded to by this memory
system.physmem.num_reads::total 444321 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 116558 # Number of write requests responded to by this memory
system.physmem.num_writes::total 116558 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 265454 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 10909504 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1439386 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 78389 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1213560 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 154626 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1371103 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15432022 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 265454 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 78389 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 154626 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 498469 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4048257 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4048257 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4048257 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 265454 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 10909504 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1439386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 78389 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1213560 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 154626 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1371103 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19480279 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 98018 # Number of read requests accepted
system.physmem.writeReqs 44365 # Number of write requests accepted
system.physmem.readBursts 98018 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 44365 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 6272576 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue
system.physmem.bytesWritten 2838464 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 6273152 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 2839360 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 42 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 6238 # Per bank write bursts
system.physmem.perBankRdBursts::1 6029 # Per bank write bursts
system.physmem.perBankRdBursts::2 6222 # Per bank write bursts
system.physmem.perBankRdBursts::3 6415 # Per bank write bursts
system.physmem.perBankRdBursts::4 5671 # Per bank write bursts
system.physmem.perBankRdBursts::5 6259 # Per bank write bursts
system.physmem.perBankRdBursts::6 6020 # Per bank write bursts
system.physmem.perBankRdBursts::7 6028 # Per bank write bursts
system.physmem.perBankRdBursts::8 6370 # Per bank write bursts
system.physmem.perBankRdBursts::9 6122 # Per bank write bursts
system.physmem.perBankRdBursts::10 6366 # Per bank write bursts
system.physmem.perBankRdBursts::11 5871 # Per bank write bursts
system.physmem.perBankRdBursts::12 5882 # Per bank write bursts
system.physmem.perBankRdBursts::13 6242 # Per bank write bursts
system.physmem.perBankRdBursts::14 6237 # Per bank write bursts
system.physmem.perBankRdBursts::15 6037 # Per bank write bursts
system.physmem.perBankWrBursts::0 2849 # Per bank write bursts
system.physmem.perBankWrBursts::1 2656 # Per bank write bursts
system.physmem.perBankWrBursts::2 2849 # Per bank write bursts
system.physmem.perBankWrBursts::3 3015 # Per bank write bursts
system.physmem.perBankWrBursts::4 2565 # Per bank write bursts
system.physmem.perBankWrBursts::5 2994 # Per bank write bursts
system.physmem.perBankWrBursts::6 2937 # Per bank write bursts
system.physmem.perBankWrBursts::7 2695 # Per bank write bursts
system.physmem.perBankWrBursts::8 3093 # Per bank write bursts
system.physmem.perBankWrBursts::9 2622 # Per bank write bursts
system.physmem.perBankWrBursts::10 2879 # Per bank write bursts
system.physmem.perBankWrBursts::11 2436 # Per bank write bursts
system.physmem.perBankWrBursts::12 2462 # Per bank write bursts
system.physmem.perBankWrBursts::13 2714 # Per bank write bursts
system.physmem.perBankWrBursts::14 2848 # Per bank write bursts
system.physmem.perBankWrBursts::15 2737 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
system.physmem.totGap 1841684892500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 98018 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 44365 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 66438 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 14086 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6897 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2022 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 974 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 959 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 558 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 553 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 609 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 552 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 526 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 458 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 405 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 401 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 400 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 400 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 398 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 398 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1794 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1779 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1773 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2070 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2377 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2093 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2091 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1839 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1836 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1834 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 2181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 2225 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 2215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2258 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1840 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 1844 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 1791 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 1859 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 1924 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 17929 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 508.069831 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 168.315652 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1577.422962 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 7580 42.28% 42.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 2972 16.58% 58.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 1827 10.19% 69.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 983 5.48% 74.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 676 3.77% 78.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 569 3.17% 81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 353 1.97% 83.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 316 1.76% 85.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 239 1.33% 86.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 212 1.18% 87.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 225 1.25% 88.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 207 1.15% 90.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 92 0.51% 90.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 80 0.45% 91.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 62 0.35% 91.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 115 0.64% 92.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 35 0.20% 92.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 50 0.28% 92.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 54 0.30% 92.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 63 0.35% 93.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 123 0.69% 94.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 74 0.41% 94.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 80 0.45% 94.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 19 0.11% 95.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 7 0.04% 95.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 37 0.21% 95.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 7 0.04% 95.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 18 0.10% 95.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 6 0.03% 95.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 9 0.05% 95.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 16 0.09% 95.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 1 0.01% 95.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 4 0.02% 95.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 12 0.07% 96.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 11 0.06% 96.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 9 0.05% 96.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 13 0.07% 97.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 2 0.01% 97.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 3 0.02% 97.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 22 0.12% 97.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 13 0.07% 97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 1 0.01% 97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611 77 0.43% 97.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995 5 0.03% 97.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 2 0.01% 97.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 8 0.04% 98.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 4 0.02% 98.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507 6 0.03% 98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635 9 0.05% 98.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699 2 0.01% 98.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 3 0.02% 98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 6 0.03% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851 1 0.01% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043 1 0.01% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 21 0.12% 98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427 1 0.01% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683 4 0.02% 99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 1 0.01% 99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8963 1 0.01% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9347 1 0.01% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539 1 0.01% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10883 2 0.01% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11011 1 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11328-11331 1 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11392-11395 1 0.01% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11779 1 0.01% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035 1 0.01% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12096-12099 1 0.01% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675 1 0.01% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12803 2 0.01% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13315 2 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211 1 0.01% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339 2 0.01% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107 1 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235 1 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 16 0.09% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15683 1 0.01% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16131 1 0.01% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 75 0.42% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 17929 # Bytes accessed per row activation
system.physmem.totQLat 2679388500 # Total ticks spent queuing
system.physmem.totMemAccLat 4331514750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 490045000 # Total ticks spent in databus transfers
system.physmem.totBankLat 1162081250 # Total ticks spent accessing banks
system.physmem.avgQLat 27338.19 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 11856.88 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 44195.07 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.16 # Average write queue length when enqueuing
system.physmem.readRowHits 89637 # Number of row buffer hits during reads
system.physmem.writeRowHits 34794 # Number of row buffer hits during writes
system.physmem.readRowHitRate 91.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.43 # Row buffer hit rate for writes
system.physmem.avgGap 12934724.60 # Average gap between requests
system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 19524219 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 44737 # Transaction distribution
system.membus.trans_dist::ReadResp 44533 # Transaction distribution
system.membus.trans_dist::WriteReq 3749 # Transaction distribution
system.membus.trans_dist::WriteResp 3749 # Transaction distribution
system.membus.trans_dist::Writeback 44365 # Transaction distribution
system.membus.trans_dist::UpgradeReq 45 # Transaction distribution
system.membus.trans_dist::UpgradeResp 45 # Transaction distribution
system.membus.trans_dist::ReadExReq 56547 # Transaction distribution
system.membus.trans_dist::ReadExResp 56547 # Transaction distribution
system.membus.trans_dist::BadAddressError 204 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13310 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189932 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 408 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 203650 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 254362 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15689 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6952704 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 6968393 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 9128201 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 35967240 # Total data (bytes)
system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 12468500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 514332500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 252500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 764298954 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 152995500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 337398 # number of replacements
system.l2c.tags.tagsinuse 65420.701532 # Cycle average of tags in use
system.l2c.tags.total_refs 2472173 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 402561 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 6.141114 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 54886.932182 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2458.825580 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2703.778525 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 528.462620 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 622.296328 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2148.830278 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 2071.576019 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.837508 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.037519 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.041256 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.008064 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.009495 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.032789 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.031610 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.998241 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 988 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 5636 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 2991 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 26143118 # Number of tag accesses
system.l2c.tags.data_accesses 26143118 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst 520243 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 493553 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 124286 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 83912 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 292769 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 239004 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1753767 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 835523 # number of Writeback hits
system.l2c.Writeback_hits::total 835523 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 92938 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 26217 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 67761 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 186916 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 520243 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 586491 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu1.data 110129 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 292769 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 306765 # number of demand (read+write) hits
system.l2c.demand_hits::total 1940683 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 520243 # number of overall hits
system.l2c.overall_hits::cpu0.data 586491 # number of overall hits
system.l2c.overall_hits::cpu1.inst 124286 # number of overall hits
system.l2c.overall_hits::cpu1.data 110129 # number of overall hits
system.l2c.overall_hits::cpu2.inst 292769 # number of overall hits
system.l2c.overall_hits::cpu2.data 306765 # number of overall hits
system.l2c.overall_hits::total 1940683 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 7643 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 238324 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2257 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 16911 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 4452 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 18142 # number of ReadReq misses
system.l2c.ReadReq_misses::total 287729 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 12 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 20 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 76060 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::cpu2.data 21606 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 115744 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 7643 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 314384 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu1.data 34989 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu2.data 39748 # number of demand (read+write) misses
system.l2c.demand_misses::total 403473 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 7643 # number of overall misses
system.l2c.overall_misses::cpu0.data 314384 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2257 # number of overall misses
system.l2c.overall_misses::cpu1.data 34989 # number of overall misses
system.l2c.overall_misses::cpu2.inst 4452 # number of overall misses
system.l2c.overall_misses::cpu2.data 39748 # number of overall misses
system.l2c.overall_misses::total 403473 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 176426247 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 1131345000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 358514250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1201423499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2867708996 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 294997 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 294997 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1254698241 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1776085226 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 3030783467 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 176426247 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2386043241 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::cpu2.data 2977508725 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 5898492463 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 176426247 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2386043241 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 358514250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 2977508725 # number of overall miss cycles
system.l2c.overall_miss_latency::total 5898492463 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 527886 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 731877 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu1.data 100823 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu2.data 257146 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2041496 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 835523 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 835523 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 168998 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 44295 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 89367 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 302660 # number of ReadExReq accesses(hits+misses)
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system.l2c.demand_accesses::cpu2.data 346513 # number of demand (read+write) accesses
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system.l2c.overall_accesses::cpu0.inst 527886 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 900875 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 126543 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 145118 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 297221 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 346513 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2344156 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014479 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.325634 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.017836 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.167730 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.014979 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.070551 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.140940 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.800000 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.740741 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.450064 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.408127 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.241767 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.382423 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014479 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.348976 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.data 0.241107 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.014979 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.114709 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.172119 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014479 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.348976 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.017836 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.241107 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.014979 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.114709 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.172119 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78168.474524 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 66899.946780 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 80528.807278 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 66223.321519 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 9966.701292 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 24583.083333 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 14749.850000 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69404.704115 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82203.333611 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 26185.231779 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 78168.474524 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 68194.096459 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 80528.807278 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 74909.648913 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 14619.299093 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 78168.474524 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 68194.096459 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 80528.807278 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 74909.648913 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 14619.299093 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 75046 # number of writebacks
system.l2c.writebacks::total 75046 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst 2257 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 16911 # number of ReadReq MSHR misses
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system.l2c.ReadReq_mshr_misses::cpu2.data 18142 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 41762 # number of ReadReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses::total 39684 # number of ReadExReq MSHR misses
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system.l2c.demand_mshr_misses::cpu1.data 34989 # number of demand (read+write) MSHR misses
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system.l2c.demand_mshr_misses::cpu2.data 39748 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 81446 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2257 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 34989 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 4452 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 39748 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 81446 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 147657253 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 919546000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 302425250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 999157501 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 2368786004 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 279009 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 279009 # number of UpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1510849774 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 2538321033 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 147657253 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1947017259 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 302425250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2510007275 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 4907107037 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 147657253 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1947017259 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu2.data 2510007275 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 4907107037 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 277801500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 291494000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 569295500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 343786500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402097500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 745884000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 621588000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 693591500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1315179500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017836 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167730 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.070551 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.020457 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408127 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241767 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.131117 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017836 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.241107 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.114709 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.034744 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017836 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.241107 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.114709 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.034744 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65421.910944 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54375.613506 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 67930.199910 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55074.275218 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 56721.086251 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23250.750000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23250.750000 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56835.449663 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69927.324539 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63963.336181 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65421.910944 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55646.553460 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 67930.199910 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63148.014366 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 60249.822422 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65421.910944 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55646.553460 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 67930.199910 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63148.014366 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 60249.822422 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.254904 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1694870354000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.254904 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 5314732731 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 5314732731 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 5324036194 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 5324036194 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 5324036194 # number of overall miss cycles
system.iocache.overall_miss_latency::total 5324036194 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127905.581705 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 127905.581705 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 127598.231132 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 127598.231132 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 168308 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 12241 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 13.749530 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435520731 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 4435520731 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 4441235194 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 4441235194 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 4441235194 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 4441235194 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262518.982659 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 262518.982659 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 4920578 # DTB read hits
system.cpu0.dtb.read_misses 6099 # DTB read misses
system.cpu0.dtb.read_acv 126 # DTB read access violations
system.cpu0.dtb.read_accesses 428233 # DTB read accesses
system.cpu0.dtb.write_hits 3510258 # DTB write hits
system.cpu0.dtb.write_misses 670 # DTB write misses
system.cpu0.dtb.write_acv 84 # DTB write access violations
system.cpu0.dtb.write_accesses 163777 # DTB write accesses
system.cpu0.dtb.data_hits 8430836 # DTB hits
system.cpu0.dtb.data_misses 6769 # DTB misses
system.cpu0.dtb.data_acv 210 # DTB access violations
system.cpu0.dtb.data_accesses 592010 # DTB accesses
system.cpu0.itb.fetch_hits 2762930 # ITB hits
system.cpu0.itb.fetch_misses 3034 # ITB misses
system.cpu0.itb.fetch_acv 104 # ITB acv
system.cpu0.itb.fetch_accesses 2765964 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 928345000 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 33879417 # Number of instructions committed
system.cpu0.committedOps 33879417 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 31738664 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 170028 # Number of float alu accesses
system.cpu0.num_func_calls 812853 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4700164 # number of instructions that are conditional controls
system.cpu0.num_int_insts 31738664 # number of integer instructions
system.cpu0.num_fp_insts 170028 # number of float instructions
system.cpu0.num_int_register_reads 44595421 # number of times the integer registers were read
system.cpu0.num_int_register_writes 23158595 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 87794 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 89338 # number of times the floating registers were written
system.cpu0.num_mem_refs 8461010 # number of memory refs
system.cpu0.num_load_insts 4941975 # Number of load instructions
system.cpu0.num_store_insts 3519035 # Number of store instructions
system.cpu0.num_idle_cycles 904626845.998199 # Number of idle cycles
system.cpu0.num_busy_cycles 23718154.001801 # Number of busy cycles
system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles
system.cpu0.Branches 5776800 # Number of branches fetched
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6418 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1819507118500 98.74% 98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 38781000 0.00% 98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 365071000 0.02% 98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 22785478000 1.24% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1842696448500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 326 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 192238 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1907
system.cpu0.kern.mode_good::user 1738
system.cpu0.kern.mode_good::idle 169
system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 29794763000 1.62% 1.62% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2592746500 0.14% 1.76% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 1810308934500 98.24% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.throughput 110459996 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 784722 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 784503 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 371354 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 150558 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 133662 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 204 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 847542 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1368014 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 2215556 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27120896 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55237129 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 82358025 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 203533320 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 11008 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 2134008000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1908780020 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 2230620167 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.iobus.throughput 1469142 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 2975 # Transaction distribution
system.iobus.trans_dist::ReadResp 2975 # Transaction distribution
system.iobus.trans_dist::WriteReq 20645 # Transaction distribution
system.iobus.trans_dist::WriteResp 20645 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8370 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 13310 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 47240 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4185 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 15689 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 1098481 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2707184 # Total data (bytes)
system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6237000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 153613694 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 9561000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17409500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.tags.replacements 951005 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.190319 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 43429541 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 951516 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 45.642471 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10399272250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.342896 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.592582 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 160.254842 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490904 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194517 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312998 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998419 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 45349405 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 45349405 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 33358489 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7831408 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2239644 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 43429541 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 33358489 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 7831408 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2239644 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 43429541 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 33358489 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 7831408 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2239644 # number of overall hits
system.cpu0.icache.overall_hits::total 43429541 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 527907 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 126543 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 313729 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 968179 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 527907 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 126543 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 313729 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 968179 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 527907 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 126543 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 313729 # number of overall misses
system.cpu0.icache.overall_misses::total 968179 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1806945253 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4430503289 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6237448542 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1806945253 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4430503289 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6237448542 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1806945253 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4430503289 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6237448542 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 33886396 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7957951 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2553373 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 44397720 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 33886396 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 7957951 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 2553373 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 44397720 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 33886396 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 7957951 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 2553373 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 44397720 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015579 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015901 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122868 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.021807 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015579 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015901 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122868 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.021807 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015579 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015901 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122868 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.021807 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14279.298365 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14122.071243 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6442.453866 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14279.298365 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14122.071243 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6442.453866 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14279.298365 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14122.071243 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6442.453866 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 3919 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 159 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.647799 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16494 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 16494 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 16494 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 16494 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 16494 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 16494 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126543 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297235 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 423778 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 126543 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 297235 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 423778 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 126543 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 297235 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 423778 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1552948747 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3649949474 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5202898221 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1552948747 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3649949474 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5202898221 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1552948747 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3649949474 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5202898221 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015901 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116409 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009545 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015901 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116409 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009545 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015901 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116409 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009545 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12272.103135 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12279.675926 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12277.414639 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12272.103135 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12279.675926 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12277.414639 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12272.103135 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12279.675926 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12277.414639 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1391788 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 13285278 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1392300 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.541965 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 249.411553 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 131.959093 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 130.627166 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.487132 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.257733 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255131 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63261634 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63261634 # Number of data accesses
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system.cpu0.dcache.WriteReq_hits::cpu2.data 1291048 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5337656 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117262 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19372 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47406 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 184040 # number of LoadLockedReq hits
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system.cpu0.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
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system.cpu0.dcache.overall_hits::cpu2.data 3687741 # number of overall hits
system.cpu0.dcache.overall_hits::total 12901893 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::total 1353573 # number of ReadReq misses
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system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6843 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 18737 # number of LoadLockedReq misses
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system.cpu0.dcache.overall_misses::cpu2.data 1129269 # number of overall misses
system.cpu0.dcache.overall_misses::total 2163380 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::total 11603967269 # number of ReadReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::total 19748913733 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28489000 # number of LoadLockedReq miss cycles
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system.cpu0.dcache.LoadLockedReq_miss_latency::total 131218249 # number of LoadLockedReq miss cycles
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system.cpu0.dcache.demand_miss_latency::total 31352881002 # number of demand (read+write) miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu2.data 27438287243 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 31352881002 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4804508 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1183842 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 2929460 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8917810 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3382883 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 877030 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 1887550 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6147463 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127004 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21524 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54249 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 202777 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126440 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21396 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51447 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 199283 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8187391 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 2060872 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 4817010 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 15065273 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8187391 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 2060872 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 4817010 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 15065273 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150304 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083348 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181865 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.151783 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049960 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050507 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.316019 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.131730 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076706 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099981 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.126141 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092402 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108843 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069372 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234434 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.143600 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108843 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069372 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234434 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.143600 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22860.582137 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17546.677570 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 8572.841856 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37450.723745 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30326.799364 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 24387.185753 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13238.382900 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15012.311705 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7003.162139 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27381.100247 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24297.388171 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14492.544538 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27381.100247 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24297.388171 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14492.544538 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 584754 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 852 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 17600 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33.224659 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 121.714286 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 835523 # number of writebacks
system.cpu0.dcache.writebacks::total 835523 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280793 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 280793 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507370 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 507370 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1423 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1423 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 788163 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 788163 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.overall_mshr_hits::total 788163 # number of overall MSHR hits
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system.cpu0.dcache.ReadReq_mshr_misses::total 350645 # number of ReadReq MSHR misses
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system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4260770982 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2625415492 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24184000 # number of LoadLockedReq MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_latency::total 10498321715 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3612135241 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6886186474 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10498321715 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296522000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310560000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607082000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364175500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426698000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790873500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660697500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737258000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397955500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083348 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086014 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039320 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050507 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047221 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021705 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099981 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099910 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037342 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032132 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032132 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20779.393135 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16909.565995 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.529801 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35258.527655 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29455.363865 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31381.923082 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11237.918216 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12112.592251 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11864.005547 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 1203332 # DTB read hits
system.cpu1.dtb.read_misses 1366 # DTB read misses
system.cpu1.dtb.read_acv 34 # DTB read access violations
system.cpu1.dtb.read_accesses 142940 # DTB read accesses
system.cpu1.dtb.write_hits 898898 # DTB write hits
system.cpu1.dtb.write_misses 183 # DTB write misses
system.cpu1.dtb.write_acv 22 # DTB write access violations
system.cpu1.dtb.write_accesses 58529 # DTB write accesses
system.cpu1.dtb.data_hits 2102230 # DTB hits
system.cpu1.dtb.data_misses 1549 # DTB misses
system.cpu1.dtb.data_acv 56 # DTB access violations
system.cpu1.dtb.data_accesses 201469 # DTB accesses
system.cpu1.itb.fetch_hits 859402 # ITB hits
system.cpu1.itb.fetch_misses 692 # ITB misses
system.cpu1.itb.fetch_acv 30 # ITB acv
system.cpu1.itb.fetch_accesses 860094 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 953617285 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 7956345 # Number of instructions committed
system.cpu1.committedOps 7956345 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 7412681 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 44901 # Number of float alu accesses
system.cpu1.num_func_calls 213028 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1020887 # number of instructions that are conditional controls
system.cpu1.num_int_insts 7412681 # number of integer instructions
system.cpu1.num_fp_insts 44901 # number of float instructions
system.cpu1.num_int_register_reads 10388601 # number of times the integer registers were read
system.cpu1.num_int_register_writes 5388855 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 24208 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 24605 # number of times the floating registers were written
system.cpu1.num_mem_refs 2109439 # number of memory refs
system.cpu1.num_load_insts 1208206 # Number of load instructions
system.cpu1.num_store_insts 901233 # Number of store instructions
system.cpu1.num_idle_cycles 922131579.439540 # Number of idle cycles
system.cpu1.num_busy_cycles 31485705.560460 # Number of busy cycles
system.cpu1.not_idle_fraction 0.033017 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.966983 # Percentage of idle cycles
system.cpu1.Branches 1300702 # Number of branches fetched
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 0
system.cpu1.kern.mode_good::user 0
system.cpu1.kern.mode_good::idle 0
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
system.cpu2.branchPred.lookups 9131296 # Number of BP lookups
system.cpu2.branchPred.condPredicted 8453261 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 124867 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 7606484 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 6524985 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 85.781880 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 282035 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 13344 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
system.cpu2.dtb.read_hits 3186348 # DTB read hits
system.cpu2.dtb.read_misses 11810 # DTB read misses
system.cpu2.dtb.read_acv 124 # DTB read access violations
system.cpu2.dtb.read_accesses 217745 # DTB read accesses
system.cpu2.dtb.write_hits 2009701 # DTB write hits
system.cpu2.dtb.write_misses 2606 # DTB write misses
system.cpu2.dtb.write_acv 109 # DTB write access violations
system.cpu2.dtb.write_accesses 82375 # DTB write accesses
system.cpu2.dtb.data_hits 5196049 # DTB hits
system.cpu2.dtb.data_misses 14416 # DTB misses
system.cpu2.dtb.data_acv 233 # DTB access violations
system.cpu2.dtb.data_accesses 300120 # DTB accesses
system.cpu2.itb.fetch_hits 370442 # ITB hits
system.cpu2.itb.fetch_misses 5628 # ITB misses
system.cpu2.itb.fetch_acv 253 # ITB acv
system.cpu2.itb.fetch_accesses 376070 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.numCycles 31313073 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 8328585 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 37006400 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 9131296 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 6807020 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 8851345 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 606644 # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles 9641968 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 10046 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 1931 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 63228 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 87070 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 2553376 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 86779 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 27379324 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.351618 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.293970 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 18527979 67.67% 67.67% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 269262 0.98% 68.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 428968 1.57% 70.22% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 5000608 18.26% 88.49% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 759354 2.77% 91.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 165275 0.60% 91.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 190932 0.70% 92.56% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 427573 1.56% 94.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 1609373 5.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 27379324 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.291613 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.181819 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 8475609 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 9724872 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 8241247 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 308907 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 382752 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 165606 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 12712 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 36612854 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 39749 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 382752 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 8834671 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 2773280 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 5760129 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 8113478 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 1269087 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 35472103 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 2436 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 230799 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 444723 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 23769376 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 44394567 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 44338159 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 52651 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 21967508 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 1801868 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 500326 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 58967 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3713170 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 3346051 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 2099971 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 366369 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 258671 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 32979578 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 619087 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 32529976 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 34753 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 2147129 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 1082645 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 436861 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 27379324 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.188122 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.575744 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 15104518 55.17% 55.17% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 3059496 11.17% 66.34% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 1557193 5.69% 72.03% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 5827645 21.28% 93.31% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 904106 3.30% 96.62% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 480512 1.76% 98.37% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 285612 1.04% 99.41% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 141433 0.52% 99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 18809 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 27379324 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 32920 13.41% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.41% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 112185 45.69% 59.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 100449 40.91% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 26864472 82.58% 82.59% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 20045 0.06% 82.65% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 8419 0.03% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 3313279 10.19% 92.87% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 2032055 6.25% 99.11% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 288046 0.89% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 32529976 # Type of FU issued
system.cpu2.iq.rate 1.038862 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 245554 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.007549 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 92485827 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 35635212 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 32132884 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 233756 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 114401 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 110529 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 32651329 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 121761 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 186414 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 413956 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 3936 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 157547 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 4151 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 27254 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 382752 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 2003866 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 204399 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 34866454 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 220221 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 3346051 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 2099971 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 549960 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 142228 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 1969 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 3936 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 63951 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 128015 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 191966 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 32372492 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 3206448 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 157484 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 1267789 # number of nop insts executed
system.cpu2.iew.exec_refs 5223192 # number of memory reference insts executed
system.cpu2.iew.exec_branches 7564928 # Number of branches executed
system.cpu2.iew.exec_stores 2016744 # Number of stores executed
system.cpu2.iew.exec_rate 1.033833 # Inst execution rate
system.cpu2.iew.wb_sent 32276755 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 32243413 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 18781769 # num instructions producing a value
system.cpu2.iew.wb_consumers 21976070 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.029711 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.854646 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 2322975 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 182226 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 177336 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 26996572 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.203754 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.846865 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 16110852 59.68% 59.68% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 2323792 8.61% 68.29% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1227035 4.55% 72.83% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 5572191 20.64% 93.47% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 501625 1.86% 95.33% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 185779 0.69% 96.02% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 177561 0.66% 96.67% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 179863 0.67% 97.34% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 717874 2.66% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 26996572 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 32497229 # Number of instructions committed
system.cpu2.commit.committedOps 32497229 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 4874519 # Number of memory references committed
system.cpu2.commit.loads 2932095 # Number of loads committed
system.cpu2.commit.membars 63814 # Number of memory barriers committed
system.cpu2.commit.branches 7417113 # Number of branches committed
system.cpu2.commit.fp_insts 109328 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 31054650 # Number of committed integer instructions.
system.cpu2.commit.function_calls 228340 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 717874 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 61024976 # The number of ROB reads
system.cpu2.rob.rob_writes 70022633 # The number of ROB writes
system.cpu2.timesIdled 244840 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 3933749 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 1746460059 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 31334430 # Number of Instructions Simulated
system.cpu2.committedOps 31334430 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 31334430 # Number of Instructions Simulated
system.cpu2.cpi 0.999318 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 0.999318 # CPI: Total CPI of All Threads
system.cpu2.ipc 1.000682 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 1.000682 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 42582766 # number of integer regfile reads
system.cpu2.int_regfile_writes 22654603 # number of integer regfile writes
system.cpu2.fp_regfile_reads 67639 # number of floating regfile reads
system.cpu2.fp_regfile_writes 67817 # number of floating regfile writes
system.cpu2.misc_regfile_reads 5361637 # number of misc regfile reads
system.cpu2.misc_regfile_writes 256988 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu2.kern.mode_good::kernel 0
system.cpu2.kern.mode_good::user 0
system.cpu2.kern.mode_good::idle 0
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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