133 lines
4.2 KiB
C++
133 lines
4.2 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Stephen Hines
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*/
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#ifndef __ARCH_ARM_PREDECODER_HH__
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#define __ARCH_ARM_PREDECODER_HH__
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#include "arch/arm/types.hh"
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#include "arch/arm/miscregs.hh"
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#include "base/types.hh"
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class ThreadContext;
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namespace ArmISA
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{
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class Predecoder
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{
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protected:
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ThreadContext * tc;
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//The extended machine instruction being generated
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ExtMachInst emi;
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MachInst data;
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bool bigThumb;
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int offset;
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ITSTATE itstate;
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public:
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void reset()
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{
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bigThumb = false;
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offset = 0;
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emi = 0;
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}
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Predecoder(ThreadContext * _tc) :
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tc(_tc), data(0)
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{
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reset();
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}
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ThreadContext * getTC()
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{
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return tc;
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}
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void
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setTC(ThreadContext * _tc)
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{
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tc = _tc;
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}
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void advanceThumbCond();
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void process();
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//Use this to give data to the predecoder. This should be used
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//when there is control flow.
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void moreBytes(Addr pc, Addr fetchPC, MachInst inst);
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//Use this to give data to the predecoder. This should be used
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//when instructions are executed in order.
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void moreBytes(MachInst machInst)
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{
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moreBytes(0, 0, machInst);
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}
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bool needMoreBytes()
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{
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return sizeof(MachInst) > offset;
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}
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bool extMachInstReady()
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{
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// The only way an instruction wouldn't be ready is if this is a
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// 32 bit ARM instruction that's not 32 bit aligned.
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return !bigThumb;
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}
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int getInstSize()
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{
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return (!emi.thumb || emi.bigThumb) ? 4 : 2;
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}
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//This returns a constant reference to the ExtMachInst to avoid a copy
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ExtMachInst getExtMachInst()
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{
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ExtMachInst thisEmi = emi;
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emi = 0;
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return thisEmi;
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}
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};
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};
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#endif // __ARCH_ARM_PREDECODER_HH__
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