gem5/mem/bus.cc
Ali Saidi bb80f71f21 fixes for new memory system
SConscript:
    comment out most devices
    add vport.cc
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
    push in alpha name space
    fix for new memory system
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Added an unimplemented fault that can be returned if a certain
    function isn't implemented
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
arch/alpha/stacktrace.cc:
arch/alpha/system.cc:
arch/alpha/tlb.hh:
arch/alpha/tru64/system.cc:
    fixed for new memory system
arch/alpha/tlb.cc:
    fixed for new memory system
    removed code that seems to have no purpose
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
    fixed for new memory system
    put in namespace AlphaISA
base/remote_gdb.cc:
    fix for new memory system
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
    create two ports one of physical accesses and one for superpage accesses
    Add functions getVirtPort() getPhysPort() delVirtPort(). To get statically
    allocated physical or virtual ports or if an execcontext is passed in
    get a dynamically allocated virtual port
dev/alpha_console.cc:
dev/alpha_console.hh:
    Redo for new memory system
dev/io_device.cc:
dev/io_device.hh:
    new I/O devices for new memory system
kern/linux/events.cc:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/tru64/dump_mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
    Arguments now in namespaces
kern/tru64/tru64_events.cc:
mem/bus.cc:
    fix for new memory syste
mem/physical.hh:
    new addressranges function
    getPort should be public
mem/port.hh:
    Add write/read methods to functional port
    update getDeviceAddrRanges to have a list of both snoops and response lists
sim/pseudo_inst.cc:
sim/system.cc:
sim/system.hh:
    Update for new mem system
sim/vptr.hh:
    comment out code and replace with panics
    This will need to be fixed at some point, but it's not easy.

--HG--
extra : convert_revision : 41f41f422cfbab3751284d55cccb6ea64a7956e2
2006-04-06 00:51:46 -04:00

129 lines
3.7 KiB
C++

/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file Definition of a bus object.
*/
#include "bus.hh"
#include "sim/builder.hh"
/** Function called by the port when the bus is recieving a Timing
* transaction.*/
bool
Bus::recvTiming(Packet &pkt, int id)
{
panic("I need to be implemented, but not right now.");
}
Port *
Bus::findPort(Addr addr, int id)
{
/* An interval tree would be a better way to do this. --ali. */
int dest_id = -1;
int i = 0;
bool found = false;
while (i < portList.size() && !found)
{
if (portList[i].range == addr) {
dest_id = portList[i].portId;
found = true;
}
}
assert(dest_id != -1 && "Unable to find destination");
// we shouldn't be sending this back to where it came from
assert(dest_id != id);
return interfaces[dest_id];
}
/** Function called by the port when the bus is recieving a Atomic
* transaction.*/
Tick
Bus::recvAtomic(Packet &pkt, int id)
{
return findPort(pkt.addr, id)->sendAtomic(pkt);
}
/** Function called by the port when the bus is recieving a Functional
* transaction.*/
void
Bus::recvFunctional(Packet &pkt, int id)
{
findPort(pkt.addr, id)->sendFunctional(pkt);
}
/** Function called by the port when the bus is recieving a status change.*/
void
Bus::recvStatusChange(Port::Status status, int id)
{
assert(status == Port:: RangeChange &&
"The other statuses need to be implemented.");
Port *port = interfaces[id];
AddrRangeList ranges;
AddrRangeList snoops;
port->getPeerAddressRanges(ranges, snoops);
// not dealing with snooping yet either
assert(snoops.size() == 0);
// or multiple ranges
assert(ranges.size() == 1);
DevMap dm;
dm.portId = id;
dm.range = ranges.front();
portList.push_back(dm);
}
void
Bus::BusPort::addressRanges(AddrRangeList &resp, AddrRangeList &snoop)
{
panic("I'm not implemented.\n");
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
Param<int> bus_id;
END_DECLARE_SIM_OBJECT_PARAMS(Bus)
BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
INIT_PARAM(bus_id, "junk bus id")
END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
CREATE_SIM_OBJECT(Bus)
{
return new Bus(getInstanceName());
}
REGISTER_SIM_OBJECT("Bus", Bus)