698767e538
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
223 lines
6.2 KiB
C++
223 lines
6.2 KiB
C++
/*
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* Copyright (c) 2011 Google
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* Copyright (c) 2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_MEMHELPERS_HH__
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#define __ARCH_X86_MEMHELPERS_HH__
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#include <array>
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#include "base/types.hh"
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#include "sim/byteswap.hh"
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#include "sim/insttracer.hh"
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namespace X86ISA
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{
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/// Initiate a read from memory in timing mode.
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template <class XC>
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Fault
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initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
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unsigned dataSize, Request::Flags flags)
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{
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return xc->initiateMemRead(addr, dataSize, flags);
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}
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static void
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getMem(PacketPtr pkt, uint64_t &mem, unsigned dataSize,
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Trace::InstRecord *traceData)
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{
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switch (dataSize) {
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case 1:
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mem = pkt->get<uint8_t>();
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break;
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case 2:
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mem = pkt->get<uint16_t>();
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break;
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case 4:
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mem = pkt->get<uint32_t>();
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break;
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case 8:
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mem = pkt->get<uint64_t>();
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break;
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default:
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panic("Unhandled size in getMem.\n");
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}
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if (traceData)
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traceData->setData(mem);
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}
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template <size_t N>
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void
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getMem(PacketPtr pkt, std::array<uint64_t, N> &mem, unsigned dataSize,
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Trace::InstRecord *traceData)
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{
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assert(dataSize >= 8);
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assert((dataSize % 8) == 0);
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int num_words = dataSize / 8;
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assert(num_words <= N);
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auto pkt_data = pkt->getConstPtr<const uint64_t>();
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for (int i = 0; i < num_words; ++i)
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mem[i] = gtoh(pkt_data[i]);
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// traceData record only has space for 64 bits, so we just record
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// the first qword
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if (traceData)
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traceData->setData(mem[0]);
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}
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template <class XC>
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Fault
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readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem,
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unsigned dataSize, Request::Flags flags)
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{
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memset(&mem, 0, sizeof(mem));
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Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
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if (fault == NoFault) {
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// If LE to LE, this is a nop, if LE to BE, the actual data ends up
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// in the right place because the LSBs where at the low addresses on
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// access. This doesn't work for BE guests.
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mem = gtoh(mem);
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if (traceData)
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traceData->setData(mem);
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}
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return fault;
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}
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template <class XC, size_t N>
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Fault
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readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr,
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std::array<uint64_t, N> &mem, unsigned dataSize,
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unsigned flags)
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{
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assert(dataSize >= 8);
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assert((dataSize % 8) == 0);
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Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
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if (fault == NoFault) {
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int num_words = dataSize / 8;
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assert(num_words <= N);
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for (int i = 0; i < num_words; ++i)
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mem[i] = gtoh(mem[i]);
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if (traceData)
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traceData->setData(mem[0]);
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}
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return fault;
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}
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template <class XC>
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Fault
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writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
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unsigned dataSize, Addr addr, Request::Flags flags,
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uint64_t *res)
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{
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if (traceData) {
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traceData->setData(mem);
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}
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mem = TheISA::htog(mem);
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return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
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}
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template <class XC, size_t N>
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Fault
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writeMemTiming(XC *xc, Trace::InstRecord *traceData,
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std::array<uint64_t, N> &mem, unsigned dataSize,
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Addr addr, unsigned flags, uint64_t *res)
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{
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assert(dataSize >= 8);
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assert((dataSize % 8) == 0);
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if (traceData) {
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traceData->setData(mem[0]);
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}
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int num_words = dataSize / 8;
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assert(num_words <= N);
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for (int i = 0; i < num_words; ++i)
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mem[i] = htog(mem[i]);
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return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
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}
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template <class XC>
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Fault
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writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
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unsigned dataSize, Addr addr, Request::Flags flags,
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uint64_t *res)
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{
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if (traceData) {
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traceData->setData(mem);
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}
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uint64_t host_mem = TheISA::htog(mem);
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Fault fault =
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xc->writeMem((uint8_t *)&host_mem, dataSize, addr, flags, res);
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if (fault == NoFault && res != NULL) {
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*res = gtoh(*res);
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}
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return fault;
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}
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template <class XC, size_t N>
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Fault
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writeMemAtomic(XC *xc, Trace::InstRecord *traceData,
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std::array<uint64_t, N> &mem, unsigned dataSize,
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Addr addr, unsigned flags, uint64_t *res)
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{
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if (traceData) {
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traceData->setData(mem[0]);
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}
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int num_words = dataSize / 8;
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assert(num_words <= N);
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for (int i = 0; i < num_words; ++i)
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mem[i] = htog(mem[i]);
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Fault fault = xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
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if (fault == NoFault && res != NULL) {
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*res = gtoh(*res);
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}
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return fault;
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}
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}
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#endif
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