fec2dea5c3
In order to support m5ops in virtualized environments, we need to use a memory mapped interface. This changeset adds support for that by reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR interface for m5ops. The mapping is done in the X86ISA::TLB::finalizePhysical() which means that it just works for all of the CPU models, including virtualized ones.
85 lines
3.4 KiB
ArmAsm
85 lines
3.4 KiB
ArmAsm
/*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Nathan Binkert
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* Ali Saidi
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*/
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#include "m5ops.h"
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#ifdef M5OP_ADDR
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/* Use the memory mapped m5op interface */
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#define TWO_BYTE_OP(name, number) \
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.globl name; \
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.func name; \
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name: \
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mov m5_mem, %r11; \
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mov $number, %rax; \
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shl $8, %rax; \
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mov 0(%r11, %rax, 1), %rax; \
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ret; \
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.endfunc;
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#else
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/* Use the magic instruction based m5op interface. This does not work
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* in virtualized environments.
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*/
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#define TWO_BYTE_OP(name, number) \
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.globl name; \
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.func name; \
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name: \
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.byte 0x0F, 0x04; \
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.word number; \
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ret; \
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.endfunc;
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#endif
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TWO_BYTE_OP(arm, arm_func)
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TWO_BYTE_OP(quiesce, quiesce_func)
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TWO_BYTE_OP(quiesceNs, quiescens_func)
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TWO_BYTE_OP(quiesceCycle, quiescecycle_func)
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TWO_BYTE_OP(quiesceTime, quiescetime_func)
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TWO_BYTE_OP(rpns, rpns_func)
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TWO_BYTE_OP(m5_exit, exit_func)
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TWO_BYTE_OP(m5_fail, fail_func)
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TWO_BYTE_OP(m5_initparam, initparam_func)
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TWO_BYTE_OP(m5_loadsymbol, loadsymbol_func)
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TWO_BYTE_OP(m5_reset_stats, resetstats_func)
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TWO_BYTE_OP(m5_dump_stats, dumpstats_func)
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TWO_BYTE_OP(m5_dumpreset_stats, dumprststats_func)
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TWO_BYTE_OP(m5_checkpoint, ckpt_func)
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TWO_BYTE_OP(m5_readfile, readfile_func)
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TWO_BYTE_OP(m5_writefile, writefile_func)
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TWO_BYTE_OP(m5_debugbreak, debugbreak_func)
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TWO_BYTE_OP(m5_switchcpu, switchcpu_func)
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TWO_BYTE_OP(m5_addsymbol, addsymbol_func)
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TWO_BYTE_OP(m5_panic, panic_func)
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TWO_BYTE_OP(m5_work_begin, work_begin_func)
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TWO_BYTE_OP(m5_work_end, work_end_func)
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