6fa936b021
Previous ARM-based simulations were limited to 8 cores due to limitations in GICv2 and earlier. This changeset adds a set of gem5-specific extensions that enable support for up to 256 cores. When the gem5 extensions are enabled, the GIC uses CPU IDs instead of a CPU bitmask in the GIC's register interface. To OS can enable the extensions by setting bit 0x200 in ICDICTR. This changeset is based on previous work by Matt Evans.
77 lines
3.3 KiB
Python
77 lines
3.3 KiB
Python
# Copyright (c) 2015 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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#
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def upgrader(cpt):
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"""The gem5 GIC extensions change the size of many GIC data
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structures. Resize them to match the new GIC."""
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import re
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if cpt.get('root','isa') != 'arm':
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return
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old_cpu_max = 8
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new_cpu_max = 256
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sgi_max = 16
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ppi_max = 16
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per_cpu_regs = (
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("iccrpr", [ "0xff", ]),
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("cpuEnabled", [ "false", ]),
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("cpuPriority", [ "0xff", ]),
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("cpuBpr", [ "0", ]),
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("cpuHighestInt", [ "1023", ]),
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("cpuPpiPending", [ "0", ]),
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("cpuPpiActive", [ "0", ] ),
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("interrupt_time", [ "0", ]),
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("*bankedIntPriority", ["0", ] * (sgi_max + ppi_max)),
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)
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new_per_cpu_regs = (
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("cpuSgiPendingExt", "0"),
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("cpuSgiActiveExt", "0"),
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)
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for sec in cpt.sections():
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if re.search('.*\.gic$', sec):
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for reg, default in per_cpu_regs:
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value = cpt.get(sec, reg).split(" ")
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assert len(value) / len(default) == old_cpu_max, \
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"GIC register size mismatch"
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value += [ " ".join(default), ] * (new_cpu_max - old_cpu_max)
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cpt.set(sec, reg, " ".join(value))
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for reg, default in new_per_cpu_regs:
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cpt.set(sec, reg, " ".join([ default, ] * new_cpu_max))
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