199 lines
5.7 KiB
C++
199 lines
5.7 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
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#define __ARCH_SPARC_ISA_TRAITS_HH__
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "sim/host.hh"
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class ExecContext;
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class FastCPU;
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//class FullCPU;
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class Checkpoint;
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class StaticInst;
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class StaticInstPtr;
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namespace BigEndianGuest {}
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#if !FULL_SYSTEM
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class SyscallReturn
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{
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public:
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template <class T>
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SyscallReturn(T v, bool s)
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{
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retval = (uint64_t)v;
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success = s;
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}
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template <class T>
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SyscallReturn(T v)
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{
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success = (v >= 0);
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retval = (uint64_t)v;
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}
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~SyscallReturn() {}
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SyscallReturn& operator=(const SyscallReturn& s)
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{
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retval = s.retval;
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success = s.success;
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return *this;
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}
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bool successful() { return success; }
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uint64_t value() { return retval; }
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private:
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uint64_t retval;
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bool success;
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};
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#endif
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namespace SparcISA
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{
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//This makes sure the big endian versions of certain functions are used.
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using namespace BigEndianGuest;
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typedef uint32_t MachInst;
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typedef uint64_t ExtMachInst;
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const int NumIntRegs = 32;
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const int NumFloatRegs = 64;
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const int NumMiscRegs = 32;
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// semantically meaningful register indices
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const int ZeroReg = 0; // architecturally meaningful
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// the rest of these depend on the ABI
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const int StackPointerReg = 14;
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const int ReturnAddressReg = 31; // post call, precall is 15
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const int ReturnValueReg = 8; // Post return, 24 is pre-return.
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const int FramePointerReg = 30;
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const int ArgumentReg0 = 8;
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const int ArgumentReg1 = 9;
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const int ArgumentReg2 = 10;
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const int ArgumentReg3 = 11;
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const int ArgumentReg4 = 12;
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const int ArgumentReg5 = 13;
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// Some OS syscall sue a second register (o1) to return a second value
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const int SyscallPseudoReturnReg = ArgumentReg1;
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//XXX These numbers are bogus
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const int MaxInstSrcRegs = 3;
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const int MaxInstDestRegs = 2;
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typedef uint64_t IntReg;
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// control register file contents
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typedef uint64_t MiscReg;
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typedef double FloatReg;
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typedef uint64_t FloatRegBits;
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//8K. This value is implmentation specific; and should probably
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//be somewhere else.
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const int LogVMPageSize = 13;
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const int VMPageSize = (1 << LogVMPageSize);
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//Why does both the previous set of constants and this one exist?
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const int PageShift = 13;
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const int PageBytes = ULL(1) << PageShift;
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const int BranchPredAddrShiftAmt = 2;
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const int WordBytes = 4;
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const int HalfwordBytes = 2;
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const int ByteBytes = 1;
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void serialize(std::ostream & os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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StaticInstPtr decodeInst(MachInst);
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// return a no-op instruction... used for instruction fetch faults
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extern const MachInst NoopMachInst;
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// Instruction address compression hooks
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inline Addr realPCToFetchPC(const Addr &addr)
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{
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return addr;
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}
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inline Addr fetchPCToRealPC(const Addr &addr)
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{
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return addr;
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}
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// the size of "fetched" instructions (not necessarily the size
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// of real instructions for PISA)
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inline size_t fetchInstSize()
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{
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return sizeof(MachInst);
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}
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param xc The execution context.
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*/
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template <class XC>
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void zeroRegisters(XC *xc);
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}
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#include "arch/sparc/regfile.hh"
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namespace SparcISA
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{
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#if !FULL_SYSTEM
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static inline void setSyscallReturn(SyscallReturn return_value,
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RegFile *regs)
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{
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// check for error condition. SPARC syscall convention is to
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// indicate success/failure in reg the carry bit of the ccr
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// and put the return value itself in the standard return value reg ().
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if (return_value.successful()) {
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// no error
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regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 0);
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regs->intRegFile[ReturnValueReg] = return_value.value();
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} else {
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// got an error, return details
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regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 1);
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regs->intRegFile[ReturnValueReg] = -return_value.value();
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}
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}
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#endif
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};
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#endif // __ARCH_SPARC_ISA_TRAITS_HH__
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