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checker
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ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
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2010-11-08 13:58:22 -06:00 |
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inorder
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Style: Replace some tabs with spaces.
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2010-12-20 16:24:40 -05:00 |
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nocpu
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SCons: Support building without an ISA
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2010-11-19 18:00:39 -06:00 |
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o3
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O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
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2010-12-07 16:19:57 -08:00 |
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ozone
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ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
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2010-11-08 13:58:22 -06:00 |
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pred
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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simple
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O3: Make all instructions that write a misc. register not perform the write until commit.
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2010-12-07 16:19:57 -08:00 |
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testers
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ruby: Converted old ruby debug calls to M5 debug calls
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2010-12-01 11:30:04 -08:00 |
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trace
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request: rename INST_READ to INST_FETCH.
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2009-04-20 18:54:02 -07:00 |
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activity.cc
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o3cpu: give a name to the activity recorder for better tracing
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2009-01-21 14:56:18 -08:00 |
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activity.hh
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o3cpu: give a name to the activity recorder for better tracing
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2009-01-21 14:56:18 -08:00 |
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base.cc
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ARM: Support switchover with hardware table walkers
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2010-12-07 16:19:57 -08:00 |
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base.hh
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O3: Make O3 support variably lengthed instructions.
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2010-11-15 19:37:03 -08:00 |
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base_dyn_inst.hh
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O3: Support squashing all state after special instruction
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2010-12-07 16:19:57 -08:00 |
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base_dyn_inst_impl.hh
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ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
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2010-11-08 13:58:22 -06:00 |
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BaseCPU.py
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X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
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2010-11-23 06:11:50 -05:00 |
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CheckerCPU.py
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python: Move more code into m5.util allow SCons to use that code.
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2009-09-22 15:24:16 -07:00 |
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cpuevent.cc
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Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
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2006-06-06 17:32:21 -04:00 |
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cpuevent.hh
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eventq: convert all usage of events to use the new API.
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2008-10-09 04:58:24 -07:00 |
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exec_context.hh
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ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
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2010-11-08 13:58:22 -06:00 |
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exetrace.cc
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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exetrace.hh
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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ExeTracer.py
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SimObjects: Clean up handling of C++ namespaces.
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2008-10-09 22:19:39 -07:00 |
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func_unit.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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func_unit.hh
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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FuncUnit.py
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
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inst_seq.hh
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build: fix compile problems pointed out by gcc 4.4
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2009-11-04 16:57:01 -08:00 |
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inteltrace.cc
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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inteltrace.hh
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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IntelTrace.py
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SimObjects: Clean up handling of C++ namespaces.
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2008-10-09 22:19:39 -07:00 |
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intr_control.cc
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style: Use the correct m5 style for things relating to interrupts.
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2008-10-21 07:12:53 -07:00 |
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intr_control.hh
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Interrupts: Inline some code and remove duplication.
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2007-11-08 10:46:41 -05:00 |
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IntrControl.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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legiontrace.cc
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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legiontrace.hh
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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LegionTrace.py
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SimObjects: Clean up handling of C++ namespaces.
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2008-10-09 22:19:39 -07:00 |
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m5legion_interface.h
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add fsr to the list of registers we are interested in
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2007-01-30 18:27:04 -05:00 |
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nativetrace.cc
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ARM: Make native trace print out what instruction caused an error.
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2009-07-27 00:54:09 -07:00 |
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nativetrace.hh
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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NativeTrace.py
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ARM: Make native trace print out what instruction caused an error.
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2009-07-27 00:54:09 -07:00 |
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op_class.hh
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
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pc_event.cc
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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pc_event.hh
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types: Move stuff for global types into src/base/types.hh
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2009-05-17 14:34:50 -07:00 |
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profile.cc
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Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
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2006-06-06 17:32:21 -04:00 |
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profile.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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quiesce_event.cc
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eventq: convert all usage of events to use the new API.
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2008-10-09 04:58:24 -07:00 |
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quiesce_event.hh
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Make the Event::description() a const function
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2008-02-06 16:32:40 -05:00 |
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SConscript
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SCons: Support building without an ISA
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2010-11-19 18:00:39 -06:00 |
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simple_thread.cc
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sim: Use forward declarations for ports.
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2010-11-08 13:58:22 -06:00 |
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simple_thread.hh
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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smt.hh
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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static_inst.cc
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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static_inst.hh
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O3: Support squashing all state after special instruction
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2010-12-07 16:19:57 -08:00 |
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thread_context.cc
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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thread_context.hh
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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thread_state.cc
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CPU: Get rid of the now unnecessary getInst/setInst family of functions.
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2010-09-13 21:58:34 -07:00 |
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thread_state.hh
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CPU: Get rid of the now unnecessary getInst/setInst family of functions.
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2010-09-13 21:58:34 -07:00 |
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translation.hh
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Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
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2010-09-13 19:26:03 -07:00 |
