Andreas Hansson f00cba34eb Mem: Make SimpleMemory single ported ... This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses.		2012-07-12 12:56:13 -04:00
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fs.py	Config: call to setWorkCountOptions() for all ISAs	2012-06-07 08:05:31 -05:00
memtest.py	Mem: Make SimpleMemory single ported	2012-07-12 12:56:13 -04:00
ruby_direct_test.py	ruby: changes how Topologies are created	2012-07-10 22:51:53 -07:00
ruby_fs.py	ruby: changes how Topologies are created	2012-07-10 22:51:53 -07:00
ruby_mem_test.py	Mem: Make SimpleMemory single ported	2012-07-12 12:56:13 -04:00
ruby_network_test.py	ruby: changes how Topologies are created	2012-07-10 22:51:53 -07:00
ruby_random_test.py	ruby: remove the cpu assumptions for the random tester	2012-07-10 22:51:54 -07:00
se.py	ruby: changes how Topologies are created	2012-07-10 22:51:53 -07:00