231 lines
7.8 KiB
C++
231 lines
7.8 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_MISCREGS_HH__
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#define __ARCH_ARM_MISCREGS_HH__
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#include "base/bitunion.hh"
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namespace ArmISA
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{
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enum ConditionCode {
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COND_EQ = 0,
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COND_NE, // 1
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COND_CS, // 2
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COND_CC, // 3
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COND_MI, // 4
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COND_PL, // 5
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COND_VS, // 6
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COND_VC, // 7
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COND_HI, // 8
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COND_LS, // 9
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COND_GE, // 10
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COND_LT, // 11
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COND_GT, // 12
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COND_LE, // 13
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COND_AL, // 14
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COND_UC // 15
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};
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enum MiscRegIndex {
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MISCREG_CPSR = 0,
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MISCREG_SPSR,
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MISCREG_SPSR_FIQ,
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MISCREG_SPSR_IRQ,
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MISCREG_SPSR_SVC,
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MISCREG_SPSR_MON,
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MISCREG_SPSR_UND,
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MISCREG_SPSR_ABT,
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MISCREG_FPSR,
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MISCREG_FPSID,
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MISCREG_FPSCR,
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MISCREG_FPEXC,
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// CP15 registers
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MISCREG_CP15_START,
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MISCREG_SCTLR = MISCREG_CP15_START,
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MISCREG_DCCISW,
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MISCREG_DCCIMVAC,
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MISCREG_CONTEXTIDR,
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MISCREG_TPIDRURW,
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MISCREG_TPIDRURO,
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MISCREG_TPIDRPRW,
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MISCREG_CP15ISB,
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MISCREG_CP15_UNIMP_START,
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MISCREG_CTR = MISCREG_CP15_UNIMP_START,
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MISCREG_TCMTR,
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MISCREG_MPUIR,
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MISCREG_MPIDR,
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MISCREG_MIDR,
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MISCREG_ID_PFR0,
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MISCREG_ID_PFR1,
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MISCREG_ID_DFR0,
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MISCREG_ID_AFR0,
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MISCREG_ID_MMFR0,
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MISCREG_ID_MMFR1,
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MISCREG_ID_MMFR2,
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MISCREG_ID_MMFR3,
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MISCREG_ID_ISAR0,
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MISCREG_ID_ISAR1,
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MISCREG_ID_ISAR2,
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MISCREG_ID_ISAR3,
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MISCREG_ID_ISAR4,
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MISCREG_ID_ISAR5,
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MISCREG_CCSIDR,
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MISCREG_CLIDR,
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MISCREG_AIDR,
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MISCREG_CSSELR,
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MISCREG_ACTLR,
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MISCREG_CPACR,
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MISCREG_DFSR,
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MISCREG_IFSR,
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MISCREG_ADFSR,
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MISCREG_AIFSR,
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MISCREG_DFAR,
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MISCREG_IFAR,
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MISCREG_DRBAR,
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MISCREG_IRBAR,
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MISCREG_DRSR,
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MISCREG_IRSR,
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MISCREG_DRACR,
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MISCREG_IRACR,
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MISCREG_RGNR,
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MISCREG_ICIALLUIS,
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MISCREG_BPIALLIS,
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MISCREG_ICIALLU,
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MISCREG_ICIMVAU,
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MISCREG_BPIALL,
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MISCREG_BPIMVA,
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MISCREG_DCIMVAC,
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MISCREG_DCISW,
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MISCREG_DCCMVAC,
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MISCREG_MCCSW,
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MISCREG_CP15DSB,
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MISCREG_CP15DMB,
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MISCREG_DCCMVAU,
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MISCREG_CP15_END,
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// Dummy indices
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MISCREG_NOP = MISCREG_CP15_END,
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MISCREG_RAZ,
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NUM_MISCREGS
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};
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MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
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unsigned crm, unsigned opc2);
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const char * const miscRegName[NUM_MISCREGS] = {
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"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
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"spsr_mon", "spsr_und", "spsr_abt",
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"fpsr", "fpsid", "fpscr", "fpexc",
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"sctlr", "dccisw", "dccimvac",
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"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
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"cp15isb", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
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"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
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"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
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"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
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"ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
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"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
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"drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
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"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
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"bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
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"cp15dsb", "cp15dmb", "dccmvau",
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"nop", "raz"
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};
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BitUnion32(CPSR)
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Bitfield<31> n;
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Bitfield<30> z;
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Bitfield<29> c;
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Bitfield<28> v;
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Bitfield<27> q;
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Bitfield<26,25> it1;
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Bitfield<24> j;
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Bitfield<19, 16> ge;
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Bitfield<15,10> it2;
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Bitfield<9> e;
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Bitfield<8> a;
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Bitfield<7> i;
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Bitfield<6> f;
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Bitfield<5> t;
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Bitfield<4, 0> mode;
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EndBitUnion(CPSR)
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// This mask selects bits of the CPSR that actually go in the CondCodes
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// integer register to allow renaming.
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static const uint32_t CondCodesMask = 0xF80F0000;
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// These otherwise unused bits of the PC are used to select a mode
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// like the J and T bits of the CPSR.
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static const Addr PcJBitShift = 33;
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static const Addr PcTBitShift = 34;
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static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
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(ULL(1) << PcTBitShift);
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BitUnion32(SCTLR)
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Bitfield<30> te; // Thumb Exception Enable
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Bitfield<29> afe; // Access flag enable
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Bitfield<28> tre; // TEX Remap bit
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Bitfield<27> nmfi;// Non-maskable fast interrupts enable
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Bitfield<25> ee; // Exception Endianness bit
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Bitfield<24> ve; // Interrupt vectors enable
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Bitfield<23> rao1;// Read as one
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Bitfield<22> u; // Alignment (now unused)
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Bitfield<21> fi; // Fast interrupts configuration enable
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Bitfield<18> rao2;// Read as one
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Bitfield<17> ha; // Hardware access flag enable
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Bitfield<16> rao3;// Read as one
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Bitfield<14> rr; // Round robin cache replacement
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Bitfield<13> v; // Base address for exception vectors
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Bitfield<12> i; // instruction cache enable
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Bitfield<11> z; // branch prediction enable bit
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Bitfield<10> sw; // Enable swp/swpb
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Bitfield<6,3> rao4;// Read as one
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Bitfield<7> b; // Endianness support (unused)
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Bitfield<2> c; // Cache enable bit
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Bitfield<1> a; // Alignment fault checking
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Bitfield<0> m; // MMU enable bit
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EndBitUnion(SCTLR)
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};
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#endif // __ARCH_ARM_MISCREGS_HH__
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