74e8abd37e
cpu/cpu_exec_context.cc:
Be sure to switch over the kernel stats so things don't get messed up. This may lead to weird stats files for sampling runs (detailed stats should be correct, regardless of which kernel stats this is defined on).
cpu/o3/cpu.cc:
Updates for switching out. Also include a bunch of debug info if needed.
cpu/o3/fetch_impl.hh:
Switch out properly.
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
Comment out unused stats (they made the stats file huge).
cpu/o3/lsq_unit.hh:
cpu/o3/lsq_unit_impl.hh:
Add in new stat.
cpu/o3/rename.hh:
Fix up for switching out.
cpu/o3/rename_impl.hh:
Fix up for switching out. Be sure to mark any Misc regs as ready if their renamed inst got squashed from being switched out.
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
Switch out fixup.
sim/eventq.hh:
Make CPU switching more immediate.
Also comment out the assertion, as it doesn't apply if we're putting it on an inst-based queue.
--HG--
extra : convert_revision : f40ed40604738993f061e0c628810ff37a920562
926 lines
25 KiB
C++
926 lines
25 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/checker/cpu.hh"
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#include "cpu/o3/lsq_unit.hh"
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#include "base/str.hh"
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template <class Impl>
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LSQUnit<Impl>::StoreCompletionEvent::StoreCompletionEvent(int store_idx,
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Event *wb_event,
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LSQUnit<Impl> *lsq_ptr)
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: Event(&mainEventQueue),
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wbEvent(wb_event),
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storeIdx(store_idx),
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lsqPtr(lsq_ptr)
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{
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this->setFlags(Event::AutoDelete);
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}
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template <class Impl>
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void
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LSQUnit<Impl>::StoreCompletionEvent::process()
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{
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DPRINTF(LSQ, "Cache miss complete for store idx:%i\n", storeIdx);
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DPRINTF(Activity, "Activity: st writeback event idx:%i\n", storeIdx);
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//lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
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if (lsqPtr->isSwitchedOut()) {
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if (wbEvent)
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delete wbEvent;
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return;
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}
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lsqPtr->cpu->wakeCPU();
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if (wbEvent) {
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wbEvent->process();
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delete wbEvent;
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}
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lsqPtr->completeStore(storeIdx);
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}
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template <class Impl>
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const char *
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LSQUnit<Impl>::StoreCompletionEvent::description()
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{
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return "LSQ store completion event";
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}
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template <class Impl>
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LSQUnit<Impl>::LSQUnit()
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: loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
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loadBlockedHandled(false)
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{
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}
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template<class Impl>
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void
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LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
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unsigned maxSQEntries, unsigned id)
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{
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DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
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switchedOut = false;
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lsqID = id;
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// Add 1 for the sentinel entry (they are circular queues).
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LQEntries = maxLQEntries + 1;
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SQEntries = maxSQEntries + 1;
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loadQueue.resize(LQEntries);
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storeQueue.resize(SQEntries);
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loadHead = loadTail = 0;
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storeHead = storeWBIdx = storeTail = 0;
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usedPorts = 0;
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cachePorts = params->cachePorts;
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dcacheInterface = params->dcacheInterface;
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memDepViolator = NULL;
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blockedLoadSeqNum = 0;
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}
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template<class Impl>
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std::string
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LSQUnit<Impl>::name() const
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{
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if (Impl::MaxThreads == 1) {
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return iewStage->name() + ".lsq";
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} else {
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return iewStage->name() + ".lsq.thread." + to_string(lsqID);
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}
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}
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template<class Impl>
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void
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LSQUnit<Impl>::regStats()
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{
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lsqForwLoads
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.name(name() + ".forwLoads")
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.desc("Number of loads that had data forwarded from stores");
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invAddrLoads
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.name(name() + ".invAddrLoads")
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.desc("Number of loads ignored due to an invalid address");
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lsqSquashedLoads
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.name(name() + ".squashedLoads")
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.desc("Number of loads squashed");
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|
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|
lsqIgnoredResponses
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.name(name() + ".ignoredResponses")
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.desc("Number of memory responses ignored because the instruction is squashed");
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lsqMemOrderViolation
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.name(name() + ".memOrderViolation")
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.desc("Number of memory ordering violations");
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|
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|
lsqSquashedStores
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.name(name() + ".squashedStores")
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.desc("Number of stores squashed");
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|
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|
invAddrSwpfs
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|
.name(name() + ".invAddrSwpfs")
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.desc("Number of software prefetches ignored due to an invalid address");
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lsqBlockedLoads
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.name(name() + ".blockedLoads")
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.desc("Number of blocked loads due to partial load-store forwarding");
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lsqRescheduledLoads
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.name(name() + ".rescheduledLoads")
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.desc("Number of loads that were rescheduled");
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lsqCacheBlocked
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.name(name() + ".cacheBlocked")
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.desc("Number of times an access to memory failed due to the cache being blocked");
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}
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template<class Impl>
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void
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LSQUnit<Impl>::clearLQ()
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{
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loadQueue.clear();
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}
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template<class Impl>
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void
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LSQUnit<Impl>::clearSQ()
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{
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storeQueue.clear();
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}
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#if 0
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template<class Impl>
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void
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LSQUnit<Impl>::setPageTable(PageTable *pt_ptr)
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{
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DPRINTF(LSQUnit, "Setting the page table pointer.\n");
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pTable = pt_ptr;
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}
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#endif
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template<class Impl>
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void
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LSQUnit<Impl>::switchOut()
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{
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switchedOut = true;
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for (int i = 0; i < loadQueue.size(); ++i)
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loadQueue[i] = NULL;
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assert(storesToWB == 0);
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while (storesToWB > 0 &&
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storeWBIdx != storeTail &&
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storeQueue[storeWBIdx].inst &&
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storeQueue[storeWBIdx].canWB) {
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if (storeQueue[storeWBIdx].size == 0 ||
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storeQueue[storeWBIdx].inst->isDataPrefetch() ||
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storeQueue[storeWBIdx].committed ||
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storeQueue[storeWBIdx].req->flags & LOCKED) {
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incrStIdx(storeWBIdx);
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continue;
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}
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assert(storeQueue[storeWBIdx].req);
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assert(!storeQueue[storeWBIdx].committed);
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MemReqPtr req = storeQueue[storeWBIdx].req;
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storeQueue[storeWBIdx].committed = true;
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req->cmd = Write;
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req->completionEvent = NULL;
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req->time = curTick;
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assert(!req->data);
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req->data = new uint8_t[64];
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memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
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DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
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"to Addr:%#x, data:%#x [sn:%lli]\n",
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storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
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req->paddr, *(req->data),
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storeQueue[storeWBIdx].inst->seqNum);
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switch(storeQueue[storeWBIdx].size) {
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case 1:
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cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
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break;
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case 2:
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cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
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break;
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case 4:
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cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
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break;
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case 8:
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cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
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break;
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default:
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panic("Unexpected store size!\n");
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}
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incrStIdx(storeWBIdx);
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}
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}
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template<class Impl>
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void
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LSQUnit<Impl>::takeOverFrom()
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|
{
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switchedOut = false;
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loads = stores = storesToWB = 0;
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|
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loadHead = loadTail = 0;
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|
storeHead = storeWBIdx = storeTail = 0;
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|
usedPorts = 0;
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|
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|
memDepViolator = NULL;
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|
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|
blockedLoadSeqNum = 0;
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|
stalled = false;
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isLoadBlocked = false;
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loadBlockedHandled = false;
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}
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|
template<class Impl>
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void
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LSQUnit<Impl>::resizeLQ(unsigned size)
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|
{
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unsigned size_plus_sentinel = size + 1;
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assert(size_plus_sentinel >= LQEntries);
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|
if (size_plus_sentinel > LQEntries) {
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while (size_plus_sentinel > loadQueue.size()) {
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DynInstPtr dummy;
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loadQueue.push_back(dummy);
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LQEntries++;
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}
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|
} else {
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LQEntries = size_plus_sentinel;
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}
|
|
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|
}
|
|
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|
template<class Impl>
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|
void
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|
LSQUnit<Impl>::resizeSQ(unsigned size)
|
|
{
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unsigned size_plus_sentinel = size + 1;
|
|
if (size_plus_sentinel > SQEntries) {
|
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while (size_plus_sentinel > storeQueue.size()) {
|
|
SQEntry dummy;
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storeQueue.push_back(dummy);
|
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SQEntries++;
|
|
}
|
|
} else {
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SQEntries = size_plus_sentinel;
|
|
}
|
|
}
|
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|
template <class Impl>
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|
void
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|
LSQUnit<Impl>::insert(DynInstPtr &inst)
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|
{
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|
assert(inst->isMemRef());
|
|
|
|
assert(inst->isLoad() || inst->isStore());
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|
|
|
if (inst->isLoad()) {
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insertLoad(inst);
|
|
} else {
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|
insertStore(inst);
|
|
}
|
|
|
|
inst->setInLSQ();
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|
}
|
|
|
|
template <class Impl>
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|
void
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|
LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
|
|
{
|
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assert((loadTail + 1) % LQEntries != loadHead);
|
|
assert(loads < LQEntries);
|
|
|
|
DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
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load_inst->readPC(), loadTail, load_inst->seqNum);
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|
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|
load_inst->lqIdx = loadTail;
|
|
|
|
if (stores == 0) {
|
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load_inst->sqIdx = -1;
|
|
} else {
|
|
load_inst->sqIdx = storeTail;
|
|
}
|
|
|
|
loadQueue[loadTail] = load_inst;
|
|
|
|
incrLdIdx(loadTail);
|
|
|
|
++loads;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
|
|
{
|
|
// Make sure it is not full before inserting an instruction.
|
|
assert((storeTail + 1) % SQEntries != storeHead);
|
|
assert(stores < SQEntries);
|
|
|
|
DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
|
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store_inst->readPC(), storeTail, store_inst->seqNum);
|
|
|
|
store_inst->sqIdx = storeTail;
|
|
store_inst->lqIdx = loadTail;
|
|
|
|
storeQueue[storeTail] = SQEntry(store_inst);
|
|
|
|
incrStIdx(storeTail);
|
|
|
|
++stores;
|
|
}
|
|
|
|
template <class Impl>
|
|
typename Impl::DynInstPtr
|
|
LSQUnit<Impl>::getMemDepViolator()
|
|
{
|
|
DynInstPtr temp = memDepViolator;
|
|
|
|
memDepViolator = NULL;
|
|
|
|
return temp;
|
|
}
|
|
|
|
template <class Impl>
|
|
unsigned
|
|
LSQUnit<Impl>::numFreeEntries()
|
|
{
|
|
unsigned free_lq_entries = LQEntries - loads;
|
|
unsigned free_sq_entries = SQEntries - stores;
|
|
|
|
// Both the LQ and SQ entries have an extra dummy entry to differentiate
|
|
// empty/full conditions. Subtract 1 from the free entries.
|
|
if (free_lq_entries < free_sq_entries) {
|
|
return free_lq_entries - 1;
|
|
} else {
|
|
return free_sq_entries - 1;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
int
|
|
LSQUnit<Impl>::numLoadsReady()
|
|
{
|
|
int load_idx = loadHead;
|
|
int retval = 0;
|
|
|
|
while (load_idx != loadTail) {
|
|
assert(loadQueue[load_idx]);
|
|
|
|
if (loadQueue[load_idx]->readyToIssue()) {
|
|
++retval;
|
|
}
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
|
|
{
|
|
// Execute a specific load.
|
|
Fault load_fault = NoFault;
|
|
|
|
DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
|
|
inst->readPC(),inst->seqNum);
|
|
|
|
// load_fault = inst->initiateAcc();
|
|
load_fault = inst->execute();
|
|
|
|
// If the instruction faulted, then we need to send it along to commit
|
|
// without the instruction completing.
|
|
if (load_fault != NoFault) {
|
|
// Send this instruction to commit, also make sure iew stage
|
|
// realizes there is activity.
|
|
iewStage->instToCommit(inst);
|
|
iewStage->activityThisCycle();
|
|
}
|
|
|
|
return load_fault;
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
|
|
{
|
|
using namespace TheISA;
|
|
// Make sure that a store exists.
|
|
assert(stores != 0);
|
|
|
|
int store_idx = store_inst->sqIdx;
|
|
|
|
DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
|
|
store_inst->readPC(), store_inst->seqNum);
|
|
|
|
// Check the recently completed loads to see if any match this store's
|
|
// address. If so, then we have a memory ordering violation.
|
|
int load_idx = store_inst->lqIdx;
|
|
|
|
Fault store_fault = store_inst->initiateAcc();
|
|
// Fault store_fault = store_inst->execute();
|
|
|
|
if (storeQueue[store_idx].size == 0) {
|
|
DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
|
|
store_inst->readPC(),store_inst->seqNum);
|
|
|
|
return store_fault;
|
|
}
|
|
|
|
assert(store_fault == NoFault);
|
|
|
|
if (store_inst->isStoreConditional()) {
|
|
// Store conditionals need to set themselves as able to
|
|
// writeback if we haven't had a fault by here.
|
|
storeQueue[store_idx].canWB = true;
|
|
|
|
++storesToWB;
|
|
}
|
|
|
|
if (!memDepViolator) {
|
|
while (load_idx != loadTail) {
|
|
// Really only need to check loads that have actually executed
|
|
// It's safe to check all loads because effAddr is set to
|
|
// InvalAddr when the dyn inst is created.
|
|
|
|
// @todo: For now this is extra conservative, detecting a
|
|
// violation if the addresses match assuming all accesses
|
|
// are quad word accesses.
|
|
|
|
// @todo: Fix this, magic number being used here
|
|
if ((loadQueue[load_idx]->effAddr >> 8) ==
|
|
(store_inst->effAddr >> 8)) {
|
|
// A load incorrectly passed this store. Squash and refetch.
|
|
// For now return a fault to show that it was unsuccessful.
|
|
memDepViolator = loadQueue[load_idx];
|
|
++lsqMemOrderViolation;
|
|
|
|
return genMachineCheckFault();
|
|
}
|
|
|
|
incrLdIdx(load_idx);
|
|
}
|
|
|
|
// If we've reached this point, there was no violation.
|
|
memDepViolator = NULL;
|
|
}
|
|
|
|
return store_fault;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitLoad()
|
|
{
|
|
assert(loadQueue[loadHead]);
|
|
|
|
DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
|
|
loadQueue[loadHead]->readPC());
|
|
|
|
loadQueue[loadHead] = NULL;
|
|
|
|
incrLdIdx(loadHead);
|
|
|
|
--loads;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
|
|
{
|
|
assert(loads == 0 || loadQueue[loadHead]);
|
|
|
|
while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
|
|
commitLoad();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
|
|
{
|
|
assert(stores == 0 || storeQueue[storeHead].inst);
|
|
|
|
int store_idx = storeHead;
|
|
|
|
while (store_idx != storeTail) {
|
|
assert(storeQueue[store_idx].inst);
|
|
// Mark any stores that are now committed and have not yet
|
|
// been marked as able to write back.
|
|
if (!storeQueue[store_idx].canWB) {
|
|
if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
|
|
break;
|
|
}
|
|
DPRINTF(LSQUnit, "Marking store as able to write back, PC "
|
|
"%#x [sn:%lli]\n",
|
|
storeQueue[store_idx].inst->readPC(),
|
|
storeQueue[store_idx].inst->seqNum);
|
|
|
|
storeQueue[store_idx].canWB = true;
|
|
|
|
++storesToWB;
|
|
}
|
|
|
|
incrStIdx(store_idx);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::writebackStores()
|
|
{
|
|
while (storesToWB > 0 &&
|
|
storeWBIdx != storeTail &&
|
|
storeQueue[storeWBIdx].inst &&
|
|
storeQueue[storeWBIdx].canWB &&
|
|
usedPorts < cachePorts) {
|
|
|
|
// Store didn't write any data so no need to write it back to
|
|
// memory.
|
|
if (storeQueue[storeWBIdx].size == 0) {
|
|
completeStore(storeWBIdx);
|
|
|
|
incrStIdx(storeWBIdx);
|
|
|
|
continue;
|
|
}
|
|
|
|
if (dcacheInterface && dcacheInterface->isBlocked()) {
|
|
DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
|
|
" is blocked!\n");
|
|
++lsqCacheBlocked;
|
|
break;
|
|
}
|
|
|
|
++usedPorts;
|
|
|
|
if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
|
|
incrStIdx(storeWBIdx);
|
|
|
|
continue;
|
|
}
|
|
|
|
assert(storeQueue[storeWBIdx].req);
|
|
assert(!storeQueue[storeWBIdx].committed);
|
|
|
|
MemReqPtr req = storeQueue[storeWBIdx].req;
|
|
storeQueue[storeWBIdx].committed = true;
|
|
|
|
req->cmd = Write;
|
|
req->completionEvent = NULL;
|
|
req->time = curTick;
|
|
assert(!req->data);
|
|
req->data = new uint8_t[64];
|
|
memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
|
|
|
|
DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
|
|
"to Addr:%#x, data:%#x [sn:%lli]\n",
|
|
storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
|
|
req->paddr, *(req->data),
|
|
storeQueue[storeWBIdx].inst->seqNum);
|
|
|
|
switch(storeQueue[storeWBIdx].size) {
|
|
case 1:
|
|
cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
|
|
break;
|
|
case 2:
|
|
cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
|
|
break;
|
|
case 4:
|
|
cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
|
|
break;
|
|
case 8:
|
|
cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
|
|
break;
|
|
default:
|
|
panic("Unexpected store size!\n");
|
|
}
|
|
|
|
// Stores other than store conditionals are completed at this
|
|
// time. Mark them as completed and, if we have a checker,
|
|
// tell it that the instruction is completed.
|
|
// @todo: Figure out what time I can say stores are complete in
|
|
// the timing memory.
|
|
if (!(req->flags & LOCKED)) {
|
|
storeQueue[storeWBIdx].inst->setCompleted();
|
|
if (cpu->checker) {
|
|
cpu->checker->tick(storeQueue[storeWBIdx].inst);
|
|
}
|
|
}
|
|
|
|
if (dcacheInterface) {
|
|
assert(!req->completionEvent);
|
|
StoreCompletionEvent *store_event = new
|
|
StoreCompletionEvent(storeWBIdx, NULL, this);
|
|
req->completionEvent = store_event;
|
|
|
|
MemAccessResult result = dcacheInterface->access(req);
|
|
|
|
if (isStalled() &&
|
|
storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
|
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
|
"load idx:%i\n",
|
|
stallingStoreIsn, stallingLoadIdx);
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
|
}
|
|
|
|
typename IEW::LdWritebackEvent *wb = NULL;
|
|
if (req->flags & LOCKED) {
|
|
// Stx_C should not generate a system port transaction
|
|
// if it misses in the cache, but that might be hard
|
|
// to accomplish without explicit cache support.
|
|
wb = new typename
|
|
IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
|
|
iewStage);
|
|
store_event->wbEvent = wb;
|
|
}
|
|
|
|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
|
DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
|
|
storeWBIdx);
|
|
|
|
DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
|
|
storeQueue[storeWBIdx].inst->seqNum);
|
|
|
|
//mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
|
|
|
|
//DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
|
|
|
|
// @todo: Increment stat here.
|
|
} else {
|
|
DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
|
|
storeWBIdx);
|
|
|
|
DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
|
|
storeQueue[storeWBIdx].inst->seqNum);
|
|
}
|
|
|
|
incrStIdx(storeWBIdx);
|
|
} else {
|
|
panic("Must HAVE DCACHE!!!!!\n");
|
|
}
|
|
}
|
|
|
|
// Not sure this should set it to 0.
|
|
usedPorts = 0;
|
|
|
|
assert(stores >= 0 && storesToWB >= 0);
|
|
}
|
|
|
|
/*template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
|
|
{
|
|
list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
|
|
mshrSeqNums.end(),
|
|
seqNum);
|
|
|
|
if (mshr_it != mshrSeqNums.end()) {
|
|
mshrSeqNums.erase(mshr_it);
|
|
DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
|
|
}
|
|
}*/
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
|
|
{
|
|
DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
|
|
"(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
|
|
|
|
int load_idx = loadTail;
|
|
decrLdIdx(load_idx);
|
|
|
|
while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
|
|
DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
|
|
"[sn:%lli]\n",
|
|
loadQueue[load_idx]->readPC(),
|
|
loadQueue[load_idx]->seqNum);
|
|
|
|
if (isStalled() && load_idx == stallingLoadIdx) {
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
stallingLoadIdx = 0;
|
|
}
|
|
|
|
// Clear the smart pointer to make sure it is decremented.
|
|
loadQueue[load_idx]->setSquashed();
|
|
loadQueue[load_idx] = NULL;
|
|
--loads;
|
|
|
|
// Inefficient!
|
|
loadTail = load_idx;
|
|
|
|
decrLdIdx(load_idx);
|
|
}
|
|
|
|
if (isLoadBlocked) {
|
|
if (squashed_num < blockedLoadSeqNum) {
|
|
isLoadBlocked = false;
|
|
loadBlockedHandled = false;
|
|
blockedLoadSeqNum = 0;
|
|
}
|
|
}
|
|
|
|
int store_idx = storeTail;
|
|
decrStIdx(store_idx);
|
|
|
|
while (stores != 0 &&
|
|
storeQueue[store_idx].inst->seqNum > squashed_num) {
|
|
// Instructions marked as can WB are already committed.
|
|
if (storeQueue[store_idx].canWB) {
|
|
break;
|
|
}
|
|
|
|
DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
|
|
"idx:%i [sn:%lli]\n",
|
|
storeQueue[store_idx].inst->readPC(),
|
|
store_idx, storeQueue[store_idx].inst->seqNum);
|
|
|
|
// I don't think this can happen. It should have been cleared
|
|
// by the stalling load.
|
|
if (isStalled() &&
|
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
|
panic("Is stalled should have been cleared by stalling load!\n");
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
}
|
|
|
|
// Clear the smart pointer to make sure it is decremented.
|
|
storeQueue[store_idx].inst->setSquashed();
|
|
storeQueue[store_idx].inst = NULL;
|
|
storeQueue[store_idx].canWB = 0;
|
|
|
|
if (storeQueue[store_idx].req) {
|
|
// There should not be a completion event if the store has
|
|
// not yet committed.
|
|
assert(!storeQueue[store_idx].req->completionEvent);
|
|
}
|
|
|
|
storeQueue[store_idx].req = NULL;
|
|
--stores;
|
|
|
|
// Inefficient!
|
|
storeTail = store_idx;
|
|
|
|
decrStIdx(store_idx);
|
|
++lsqSquashedStores;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::completeStore(int store_idx)
|
|
{
|
|
assert(storeQueue[store_idx].inst);
|
|
storeQueue[store_idx].completed = true;
|
|
--storesToWB;
|
|
// A bit conservative because a store completion may not free up entries,
|
|
// but hopefully avoids two store completions in one cycle from making
|
|
// the CPU tick twice.
|
|
cpu->activityThisCycle();
|
|
|
|
if (store_idx == storeHead) {
|
|
do {
|
|
incrStIdx(storeHead);
|
|
|
|
--stores;
|
|
} while (storeQueue[storeHead].completed &&
|
|
storeHead != storeTail);
|
|
|
|
iewStage->updateLSQNextCycle = true;
|
|
}
|
|
|
|
DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
|
|
"idx:%i\n",
|
|
storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
|
|
|
|
if (isStalled() &&
|
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
|
"load idx:%i\n",
|
|
stallingStoreIsn, stallingLoadIdx);
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
|
}
|
|
|
|
storeQueue[store_idx].inst->setCompleted();
|
|
|
|
// Tell the checker we've completed this instruction. Some stores
|
|
// may get reported twice to the checker, but the checker can
|
|
// handle that case.
|
|
if (cpu->checker) {
|
|
cpu->checker->tick(storeQueue[store_idx].inst);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::incrStIdx(int &store_idx)
|
|
{
|
|
if (++store_idx >= SQEntries)
|
|
store_idx = 0;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::decrStIdx(int &store_idx)
|
|
{
|
|
if (--store_idx < 0)
|
|
store_idx += SQEntries;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::incrLdIdx(int &load_idx)
|
|
{
|
|
if (++load_idx >= LQEntries)
|
|
load_idx = 0;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::decrLdIdx(int &load_idx)
|
|
{
|
|
if (--load_idx < 0)
|
|
load_idx += LQEntries;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::dumpInsts()
|
|
{
|
|
cprintf("Load store queue: Dumping instructions.\n");
|
|
cprintf("Load queue size: %i\n", loads);
|
|
cprintf("Load queue: ");
|
|
|
|
int load_idx = loadHead;
|
|
|
|
while (load_idx != loadTail && loadQueue[load_idx]) {
|
|
cprintf("%#x ", loadQueue[load_idx]->readPC());
|
|
|
|
incrLdIdx(load_idx);
|
|
}
|
|
|
|
cprintf("Store queue size: %i\n", stores);
|
|
cprintf("Store queue: ");
|
|
|
|
int store_idx = storeHead;
|
|
|
|
while (store_idx != storeTail && storeQueue[store_idx].inst) {
|
|
cprintf("%#x ", storeQueue[store_idx].inst->readPC());
|
|
|
|
incrStIdx(store_idx);
|
|
}
|
|
|
|
cprintf("\n");
|
|
}
|