716ceb6c10
arch/alpha/isa_traits.hh:
Add in clear functions.
cpu/base.cc:
cpu/base.hh:
Add in CPU progress event.
cpu/base_dyn_inst.hh:
Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
Allow for progress intervals.
cpu/o3/tournament_pred.cc:
Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
Fixes.
cpu/ozone/cpu_builder.cc:
Allow progress interval.
cpu/ozone/front_end_impl.hh:
Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
Remove this.
python/m5/objects/BaseCPU.py:
Add progress interval.
python/m5/objects/Root.py:
Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
Add in stats reset.
--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e
712 lines
24 KiB
C++
712 lines
24 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_BASE_DYN_INST_HH__
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#define __CPU_BASE_DYN_INST_HH__
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#include <list>
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#include <string>
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#include "base/fast_alloc.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/static_inst.hh"
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#include "encumbered/cpu/full/op_class.hh"
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#include "mem/functional/memory_control.hh"
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#include "sim/system.hh"
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/*
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#include "encumbered/cpu/full/bpred_update.hh"
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#include "encumbered/cpu/full/spec_memory.hh"
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#include "encumbered/cpu/full/spec_state.hh"
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#include "encumbered/mem/functional/main.hh"
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*/
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/**
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* @file
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* Defines a dynamic instruction context.
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*/
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// Forward declaration.
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class StaticInstPtr;
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template <class Impl>
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class BaseDynInst : public FastAlloc, public RefCounted
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{
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public:
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// Typedef for the CPU.
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typedef typename Impl::FullCPU FullCPU;
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typedef typename FullCPU::ImplState ImplState;
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// Binary machine instruction type.
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typedef TheISA::MachInst MachInst;
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// Extended machine instruction type
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typedef TheISA::ExtMachInst ExtMachInst;
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// Logical register index type.
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typedef TheISA::RegIndex RegIndex;
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// Integer register index type.
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typedef TheISA::IntReg IntReg;
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// The DynInstPtr type.
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typedef typename Impl::DynInstPtr DynInstPtr;
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// The list of instructions iterator type.
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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enum {
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MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
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MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
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};
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/** The StaticInst used by this BaseDynInst. */
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StaticInstPtr staticInst;
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////////////////////////////////////////////
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//
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// INSTRUCTION EXECUTION
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//
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////////////////////////////////////////////
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/** InstRecord that tracks this instructions. */
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Trace::InstRecord *traceData;
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/**
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* Does a read to a given address.
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* @param addr The address to read.
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* @param data The read's data is written into this parameter.
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* @param flags The request's flags.
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* @return Returns any fault due to the read.
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*/
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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/**
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* Does a write to a given address.
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* @param data The data to be written.
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* @param addr The address to write to.
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* @param flags The request's flags.
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* @param res The result of the write (for load locked/store conditionals).
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* @return Returns any fault due to the write.
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*/
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template <class T>
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Fault write(T data, Addr addr, unsigned flags,
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uint64_t *res);
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void prefetch(Addr addr, unsigned flags);
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void writeHint(Addr addr, int size, unsigned flags);
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Fault copySrcTranslate(Addr src);
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Fault copy(Addr dest);
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/** @todo: Consider making this private. */
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public:
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/** The sequence number of the instruction. */
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InstSeqNum seqNum;
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enum Status {
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IqEntry, /// Instruction is in the IQ
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RobEntry, /// Instruction is in the ROB
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LsqEntry, /// Instruction is in the LSQ
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Completed, /// Instruction has completed
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ResultReady, /// Instruction has its result
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CanIssue, /// Instruction can issue and execute
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Issued, /// Instruction has issued
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Executed, /// Instruction has executed
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CanCommit, /// Instruction can commit
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AtCommit, /// Instruction has reached commit
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Committed, /// Instruction has committed
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Squashed, /// Instruction is squashed
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SquashedInIQ, /// Instruction is squashed in the IQ
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SquashedInLSQ, /// Instruction is squashed in the LSQ
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SquashedInROB, /// Instruction is squashed in the ROB
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RecoverInst, /// Is a recover instruction
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BlockingInst, /// Is a blocking instruction
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ThreadsyncWait, /// Is a thread synchronization instruction
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SerializeBefore, /// Needs to serialize on
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/// instructions ahead of it
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SerializeAfter, /// Needs to serialize instructions behind it
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SerializeHandled, /// Serialization has been handled
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NumStatus
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};
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/** The status of this BaseDynInst. Several bits can be set. */
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std::bitset<NumStatus> status;
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/** The thread this instruction is from. */
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short threadNumber;
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/** data address space ID, for loads & stores. */
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short asid;
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/** How many source registers are ready. */
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unsigned readyRegs;
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/** Pointer to the FullCPU object. */
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FullCPU *cpu;
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/** Pointer to the exec context. */
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ImplState *thread;
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/** The kind of fault this instruction has generated. */
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Fault fault;
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/** The memory request. */
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MemReqPtr req;
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/** The effective virtual address (lds & stores only). */
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Addr effAddr;
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/** The effective physical address. */
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Addr physEffAddr;
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/** Effective virtual address for a copy source. */
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Addr copySrcEffAddr;
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/** Effective physical address for a copy source. */
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Addr copySrcPhysEffAddr;
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/** The memory request flags (from translation). */
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unsigned memReqFlags;
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/** The size of the data to be stored. */
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int storeSize;
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/** The data to be stored. */
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IntReg storeData;
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union Result {
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uint64_t integer;
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// float fp;
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double dbl;
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};
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/** The result of the instruction; assumes for now that there's only one
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* destination register.
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*/
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Result instResult;
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/** PC of this instruction. */
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Addr PC;
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/** Next non-speculative PC. It is not filled in at fetch, but rather
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* once the target of the branch is truly known (either decode or
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* execute).
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*/
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Addr nextPC;
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/** Predicted next PC. */
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Addr predPC;
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/** Count of total number of dynamic instructions. */
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static int instcount;
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#ifdef DEBUG
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void dumpSNList();
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#endif
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/** Whether or not the source register is ready.
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* @todo: Not sure this should be here vs the derived class.
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*/
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bool _readySrcRegIdx[MaxInstSrcRegs];
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public:
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/** BaseDynInst constructor given a binary instruction.
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* @param inst The binary instruction.
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* @param PC The PC of the instruction.
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* @param pred_PC The predicted next PC.
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* @param seq_num The sequence number of the instruction.
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* @param cpu Pointer to the instruction's CPU.
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*/
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BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
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FullCPU *cpu);
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/** BaseDynInst constructor given a StaticInst pointer.
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* @param _staticInst The StaticInst for this BaseDynInst.
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*/
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BaseDynInst(StaticInstPtr &_staticInst);
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/** BaseDynInst destructor. */
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~BaseDynInst();
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private:
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/** Function to initialize variables in the constructors. */
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void initVars();
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public:
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/**
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* @todo: Make this function work; currently it is a dummy function.
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* @param fault Last fault.
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* @param cmd Last command.
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* @param addr Virtual address of access.
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* @param p Memory accessed.
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* @param nbytes Access size.
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*/
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void
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trace_mem(Fault fault,
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MemCmd cmd,
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Addr addr,
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void *p,
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int nbytes);
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/** Dumps out contents of this BaseDynInst. */
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void dump();
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/** Dumps out contents of this BaseDynInst into given string. */
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void dump(std::string &outstring);
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/** Returns the fault type. */
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Fault getFault() { return fault; }
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/** Checks whether or not this instruction has had its branch target
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* calculated yet. For now it is not utilized and is hacked to be
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* always false.
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* @todo: Actually use this instruction.
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*/
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bool doneTargCalc() { return false; }
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/** Returns the next PC. This could be the speculative next PC if it is
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* called prior to the actual branch target being calculated.
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*/
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Addr readNextPC() { return nextPC; }
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/** Set the predicted target of this current instruction. */
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void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
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/** Returns the predicted target of the branch. */
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Addr readPredTarg() { return predPC; }
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/** Returns whether the instruction was predicted taken or not. */
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bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
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/** Returns whether the instruction mispredicted. */
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bool mispredicted() { return predPC != nextPC; }
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//
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// Instruction types. Forward checks to StaticInst object.
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//
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bool isNop() const { return staticInst->isNop(); }
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bool isMemRef() const { return staticInst->isMemRef(); }
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bool isLoad() const { return staticInst->isLoad(); }
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bool isStore() const { return staticInst->isStore(); }
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bool isStoreConditional() const
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{ return staticInst->isStoreConditional(); }
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bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
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bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
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bool isCopy() const { return staticInst->isCopy(); }
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bool isInteger() const { return staticInst->isInteger(); }
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bool isFloating() const { return staticInst->isFloating(); }
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bool isControl() const { return staticInst->isControl(); }
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bool isCall() const { return staticInst->isCall(); }
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bool isReturn() const { return staticInst->isReturn(); }
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bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
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bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
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bool isCondCtrl() const { return staticInst->isCondCtrl(); }
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bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
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bool isThreadSync() const { return staticInst->isThreadSync(); }
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bool isSerializing() const { return staticInst->isSerializing(); }
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bool isSerializeBefore() const
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{ return staticInst->isSerializeBefore() || status[SerializeBefore]; }
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bool isSerializeAfter() const
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{ return staticInst->isSerializeAfter() || status[SerializeAfter]; }
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bool isMemBarrier() const { return staticInst->isMemBarrier(); }
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bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
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bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
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bool isQuiesce() const { return staticInst->isQuiesce(); }
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bool isIprAccess() const { return staticInst->isIprAccess(); }
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bool isUnverifiable() const { return staticInst->isUnverifiable(); }
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/** Temporarily sets this instruction as a serialize before instruction. */
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void setSerializeBefore() { status.set(SerializeBefore); }
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/** Clears the serializeBefore part of this instruction. */
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void clearSerializeBefore() { status.reset(SerializeBefore); }
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/** Checks if this serializeBefore is only temporarily set. */
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bool isTempSerializeBefore() { return status[SerializeBefore]; }
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/** Temporarily sets this instruction as a serialize after instruction. */
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void setSerializeAfter() { status.set(SerializeAfter); }
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/** Clears the serializeAfter part of this instruction.*/
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void clearSerializeAfter() { status.reset(SerializeAfter); }
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/** Checks if this serializeAfter is only temporarily set. */
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bool isTempSerializeAfter() { return status[SerializeAfter]; }
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/** Sets the serialization part of this instruction as handled. */
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void setSerializeHandled() { status.set(SerializeHandled); }
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/** Checks if the serialization part of this instruction has been
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* handled. This does not apply to the temporary serializing
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* state; it only applies to this instruction's own permanent
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* serializing state.
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*/
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bool isSerializeHandled() { return status[SerializeHandled]; }
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/** Returns the opclass of this instruction. */
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OpClass opClass() const { return staticInst->opClass(); }
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/** Returns the branch target address. */
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Addr branchTarget() const { return staticInst->branchTarget(PC); }
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/** Returns the number of source registers. */
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int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
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/** Returns the number of destination registers. */
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int8_t numDestRegs() const { return staticInst->numDestRegs(); }
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// the following are used to track physical register usage
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// for machines with separate int & FP reg files
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int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
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int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
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/** Returns the logical register index of the i'th destination register. */
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RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
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/** Returns the logical register index of the i'th source register. */
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RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
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/** Returns the result of an integer instruction. */
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uint64_t readIntResult() { return instResult.integer; }
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/** Returns the result of a floating point instruction. */
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float readFloatResult() { return (float)instResult.dbl; }
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/** Returns the result of a floating point (double) instruction. */
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double readDoubleResult() { return instResult.dbl; }
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void setIntReg(const StaticInst *si, int idx, uint64_t val)
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{
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instResult.integer = val;
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}
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void setFloatRegSingle(const StaticInst *si, int idx, float val)
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{
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// instResult.fp = val;
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instResult.dbl = (double)val;
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}
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void setFloatRegDouble(const StaticInst *si, int idx, double val)
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{
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instResult.dbl = val;
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}
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void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
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{
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instResult.integer = val;
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}
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/** Records that one of the source registers is ready. */
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void markSrcRegReady();
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/** Marks a specific register as ready. */
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void markSrcRegReady(RegIndex src_idx);
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/** Returns if a source register is ready. */
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bool isReadySrcRegIdx(int idx) const
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{
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return this->_readySrcRegIdx[idx];
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}
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/** Sets this instruction as completed. */
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void setCompleted() { status.set(Completed); }
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/** Returns whether or not this instruction is completed. */
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bool isCompleted() const { return status[Completed]; }
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/** Marks the result as ready. */
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void setResultReady() { status.set(ResultReady); }
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/** Returns whether or not the result is ready. */
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bool isResultReady() const { return status[ResultReady]; }
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/** Sets this instruction as ready to issue. */
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void setCanIssue() { status.set(CanIssue); }
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/** Returns whether or not this instruction is ready to issue. */
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bool readyToIssue() const { return status[CanIssue]; }
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/** Sets this instruction as issued from the IQ. */
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void setIssued() { status.set(Issued); }
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/** Returns whether or not this instruction has issued. */
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bool isIssued() const { return status[Issued]; }
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/** Sets this instruction as executed. */
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void setExecuted() { status.set(Executed); }
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/** Returns whether or not this instruction has executed. */
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bool isExecuted() const { return status[Executed]; }
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/** Sets this instruction as ready to commit. */
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void setCanCommit() { status.set(CanCommit); }
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/** Clears this instruction as being ready to commit. */
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void clearCanCommit() { status.reset(CanCommit); }
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/** Returns whether or not this instruction is ready to commit. */
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bool readyToCommit() const { return status[CanCommit]; }
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void setAtCommit() { status.set(AtCommit); }
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bool isAtCommit() { return status[AtCommit]; }
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/** Sets this instruction as committed. */
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void setCommitted() { status.set(Committed); }
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/** Returns whether or not this instruction is committed. */
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bool isCommitted() const { return status[Committed]; }
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/** Sets this instruction as squashed. */
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void setSquashed() { status.set(Squashed); }
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/** Returns whether or not this instruction is squashed. */
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bool isSquashed() const { return status[Squashed]; }
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//Instruction Queue Entry
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//-----------------------
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/** Sets this instruction as a entry the IQ. */
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void setInIQ() { status.set(IqEntry); }
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/** Sets this instruction as a entry the IQ. */
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void clearInIQ() { status.reset(IqEntry); }
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/** Returns whether or not this instruction has issued. */
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bool isInIQ() const { return status[IqEntry]; }
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/** Sets this instruction as squashed in the IQ. */
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void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
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/** Returns whether or not this instruction is squashed in the IQ. */
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bool isSquashedInIQ() const { return status[SquashedInIQ]; }
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|
|
|
|
|
//Load / Store Queue Functions
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//-----------------------
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/** Sets this instruction as a entry the LSQ. */
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void setInLSQ() { status.set(LsqEntry); }
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|
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/** Sets this instruction as a entry the LSQ. */
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void removeInLSQ() { status.reset(LsqEntry); }
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/** Returns whether or not this instruction is in the LSQ. */
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bool isInLSQ() const { return status[LsqEntry]; }
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|
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/** Sets this instruction as squashed in the LSQ. */
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|
void setSquashedInLSQ() { status.set(SquashedInLSQ);}
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/** Returns whether or not this instruction is squashed in the LSQ. */
|
|
bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
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|
|
|
|
//Reorder Buffer Functions
|
|
//-----------------------
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|
/** Sets this instruction as a entry the ROB. */
|
|
void setInROB() { status.set(RobEntry); }
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|
|
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/** Sets this instruction as a entry the ROB. */
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|
void clearInROB() { status.reset(RobEntry); }
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|
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/** Returns whether or not this instruction is in the ROB. */
|
|
bool isInROB() const { return status[RobEntry]; }
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|
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/** Sets this instruction as squashed in the ROB. */
|
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void setSquashedInROB() { status.set(SquashedInROB); }
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|
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/** Returns whether or not this instruction is squashed in the ROB. */
|
|
bool isSquashedInROB() const { return status[SquashedInROB]; }
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|
|
|
/** Read the PC of this instruction. */
|
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const Addr readPC() const { return PC; }
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|
|
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/** Set the next PC of this instruction (its actual target). */
|
|
void setNextPC(uint64_t val)
|
|
{
|
|
nextPC = val;
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|
// instResult.integer = val;
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|
}
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|
|
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void setASID(short addr_space_id) { asid = addr_space_id; }
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|
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void setThread(unsigned tid) { threadNumber = tid; }
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|
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void setState(ImplState *state) { thread = state; }
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|
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/** Returns the exec context.
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|
* @todo: Remove this once the ExecContext is no longer used.
|
|
*/
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|
ExecContext *xcBase() { return thread->getXCProxy(); }
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private:
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/** Instruction effective address.
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|
* @todo: Consider if this is necessary or not.
|
|
*/
|
|
Addr instEffAddr;
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|
|
|
/** Whether or not the effective address calculation is completed.
|
|
* @todo: Consider if this is necessary or not.
|
|
*/
|
|
bool eaCalcDone;
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|
|
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public:
|
|
/** Sets the effective address. */
|
|
void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
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|
|
|
/** Returns the effective address. */
|
|
const Addr &getEA() const { return req->vaddr; }
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|
|
|
/** Returns whether or not the eff. addr. calculation has been completed. */
|
|
bool doneEACalc() { return eaCalcDone; }
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|
|
|
/** Returns whether or not the eff. addr. source registers are ready. */
|
|
bool eaSrcsReady();
|
|
|
|
/** Whether or not the memory operation is done. */
|
|
bool memOpDone;
|
|
|
|
public:
|
|
/** Load queue index. */
|
|
int16_t lqIdx;
|
|
|
|
/** Store queue index. */
|
|
int16_t sqIdx;
|
|
|
|
/** Iterator pointing to this BaseDynInst in the list of all insts. */
|
|
ListIt instListIt;
|
|
|
|
/** Returns iterator to this instruction in the list of all insts. */
|
|
ListIt &getInstListIt() { return instListIt; }
|
|
|
|
/** Sets iterator for this instruction in the list of all insts. */
|
|
void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
|
|
};
|
|
|
|
template<class Impl>
|
|
template<class T>
|
|
inline Fault
|
|
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
|
|
{
|
|
if (status[Executed]) {
|
|
fault = cpu->read(req, data, lqIdx);
|
|
return fault;
|
|
}
|
|
|
|
req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
|
|
req->asid = asid;
|
|
req->thread_num = threadNumber;
|
|
req->pc = this->PC;
|
|
|
|
if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
|
|
TheISA::VMPageSize) {
|
|
return TheISA::genAlignmentFault();
|
|
}
|
|
|
|
fault = cpu->translateDataReadReq(req);
|
|
|
|
effAddr = req->vaddr;
|
|
physEffAddr = req->paddr;
|
|
memReqFlags = req->flags;
|
|
|
|
if (fault == NoFault) {
|
|
#if FULL_SYSTEM
|
|
if (cpu->system->memctrl->badaddr(physEffAddr)) {
|
|
fault = TheISA::genMachineCheckFault();
|
|
data = (T)-1;
|
|
this->setExecuted();
|
|
} else {
|
|
fault = cpu->read(req, data, lqIdx);
|
|
}
|
|
#else
|
|
fault = cpu->read(req, data, lqIdx);
|
|
#endif
|
|
} else {
|
|
// Return a fixed value to keep simulation deterministic even
|
|
// along misspeculated paths.
|
|
data = (T)-1;
|
|
|
|
// Commit will have to clean up whatever happened. Set this
|
|
// instruction as executed.
|
|
this->setExecuted();
|
|
}
|
|
|
|
if (traceData) {
|
|
traceData->setAddr(addr);
|
|
traceData->setData(data);
|
|
}
|
|
|
|
return fault;
|
|
}
|
|
|
|
template<class Impl>
|
|
template<class T>
|
|
inline Fault
|
|
BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
if (traceData) {
|
|
traceData->setAddr(addr);
|
|
traceData->setData(data);
|
|
}
|
|
|
|
req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
|
|
|
|
req->asid = asid;
|
|
req->thread_num = threadNumber;
|
|
req->pc = this->PC;
|
|
|
|
if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
|
|
TheISA::VMPageSize) {
|
|
return TheISA::genAlignmentFault();
|
|
}
|
|
|
|
fault = cpu->translateDataWriteReq(req);
|
|
|
|
effAddr = req->vaddr;
|
|
physEffAddr = req->paddr;
|
|
memReqFlags = req->flags;
|
|
|
|
if (fault == NoFault) {
|
|
#if FULL_SYSTEM
|
|
if (cpu->system->memctrl->badaddr(physEffAddr)) {
|
|
fault = TheISA::genMachineCheckFault();
|
|
} else {
|
|
fault = cpu->write(req, data, sqIdx);
|
|
}
|
|
#else
|
|
fault = cpu->write(req, data, sqIdx);
|
|
#endif
|
|
}
|
|
|
|
if (res) {
|
|
// always return some result to keep misspeculated paths
|
|
// (which will ignore faults) deterministic
|
|
*res = (fault == NoFault) ? req->result : 0;
|
|
}
|
|
|
|
return fault;
|
|
}
|
|
|
|
#endif // __CPU_BASE_DYN_INST_HH__
|