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gem5/src/sim
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Andreas Sandberg db5c9a5f90 base: Redesign internal frame buffer handling 
Currently, frame buffer handling in gem5 is quite ad hoc. In practice,
we pass around naked pointers to raw pixel data and expect consumers
to convert frame buffers using the (broken) VideoConverter.

This changeset completely redesigns the way we handle frame buffers
internally. In summary, it fixes several color conversion bugs, adds
support for more color formats (e.g., big endian), and makes the code
base easier to follow.

In the new world, gem5 always represents pixel data using the Pixel
struct when pixels need to be passed between different classes (e.g.,
a display controller and the VNC server). Producers of entire frames
(e.g., display controllers) should use the FrameBuffer class to
represent a frame.

Frame producers are expected to create one instance of the FrameBuffer
class in their constructors and register it with its consumers
once. Consumers are expected to check the dimensions of the frame
buffer when they consume it.

Conversion between the external representation and the internal
representation is supported for all common "true color" RGB formats of
up to 32-bit color depth. The external pixel representation is
expected to be between 1 and 4 bytes in either big endian or little
endian. Color channels are assumed to be contiguous ranges of bits
within each pixel word. The external pixel value is scaled to an 8-bit
internal representation using a floating multiplication to map it to
the entire 8-bit range.
2015-05-23 13:37:03 +01:00
..
probe sim: Add typedefs for PMU probe points 2014-10-16 05:49:38 -04:00
arguments.cc GetArgument: Rework getArgument so that X86_FS compiles again. 2010-10-15 23:57:06 -07:00
arguments.hh dev: Use shared_ptr for Arguments::Data 2014-10-16 05:49:45 -04:00
async.cc base: Fix race in PollQueue and remove SIGALRM workaround 2013-11-29 14:36:10 +01:00
async.hh base: Fix race in PollQueue and remove SIGALRM workaround 2013-11-29 14:36:10 +01:00
byteswap.hh base: Redesign internal frame buffer handling 2015-05-23 13:37:03 +01:00
clock_domain.cc energy: Small extentions and fixes for DVFS handler 2014-06-16 14:59:44 +01:00
clock_domain.hh energy: Small extentions and fixes for DVFS handler 2014-06-16 14:59:44 +01:00
ClockDomain.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
clocked_object.hh sim: More rigorous clocking comments 2014-06-09 22:01:16 -05:00
ClockedObject.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
core.cc sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
core.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
cxx_config.cc config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_config.hh config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_config_ini.cc config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_config_ini.hh config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_manager.cc config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_manager.hh config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
debug.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
debug.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
drain.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
drain.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
dvfs_handler.cc energy: Small extentions and fixes for DVFS handler 2014-06-16 14:59:44 +01:00
dvfs_handler.hh energy: Tighter checking of levels for DFS systems 2014-08-12 19:00:44 +01:00
DVFSHandler.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
emul_driver.hh syscall_emul: add EmulatedDriver object 2014-10-22 15:53:34 -07:00
eventq.cc misc: Fix a bunch of minor issues identified by static analysis 2014-09-27 09:08:29 -04:00
eventq.hh sim: Remove test for non-NULL this in Event 2015-02-03 14:25:48 -05:00
eventq_impl.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
faults.cc cpu: Remove all notion that we know when the cpu is misspeculating. 2015-01-25 07:22:26 -05:00
faults.hh arch: Use shared_ptr for all Faults 2014-10-16 05:49:51 -04:00
full_system.hh clang: Fix recently introduced clang compilation errors 2012-03-19 06:35:04 -04:00
global_event.cc sim: Fix resource leak in BaseGlobalEvent 2014-09-09 04:36:32 -04:00
global_event.hh sim: Fix resource leak in BaseGlobalEvent 2014-09-09 04:36:32 -04:00
init.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
init.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
init_signals.cc sim: EventQueue wakeup on events scheduled outside the event loop 2014-10-16 05:49:53 -04:00
init_signals.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
insttracer.hh sim: Clean up InstRecord 2015-01-25 07:22:44 -05:00
InstTracer.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
main.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
process.cc arch, base, dev, kern, sym: FreeBSD support 2015-04-29 22:35:23 -05:00
process.hh sim: Use NULL instead of None for testing filenames. 2015-04-13 17:33:57 -05:00
Process.py mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
process_impl.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
pseudo_inst.cc kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00
pseudo_inst.hh sim: Add a helper function to execute pseudo instructions 2013-04-22 13:20:32 -04:00
py_interact.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
py_interact.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
root.cc sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
root.hh sim: Provide a framework for detecting out of data checkpoints and migrating them. 2012-06-05 01:23:10 -04:00
Root.py sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
SConscript sim: Move the BaseTLB to src/arch/generic/ 2015-02-11 10:23:27 -05:00
serialize.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
serialize.hh sim: Add support for serializing BitUnionXX 2014-10-16 05:49:37 -04:00
sim_events.cc sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
sim_events.hh sim: Update limit_event reuse to final version 2015-03-26 11:16:44 -04:00
sim_exit.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
sim_object.cc misc: Fix issues identified by static analysis 2014-10-01 08:05:54 -04:00
sim_object.hh misc: Fix issues identified by static analysis 2014-10-01 08:05:54 -04:00
simulate.cc sim: Update limit_event reuse to final version 2015-03-26 11:16:44 -04:00
simulate.hh sim: Update limit_event reuse to final version 2015-03-26 11:16:44 -04:00
stat_control.cc style: Fix line continuation, especially in debug messages 2014-09-12 10:22:47 -04:00
stat_control.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
stat_register.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
stat_register.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
stats.hh stats: make simTicks and simFreq accessible from stats.hh 2010-04-18 13:23:25 -07:00
sub_system.cc config: Add SubSystem container for simobjects 2014-08-10 05:39:16 -04:00
sub_system.hh config: Add SubSystem container for simobjects 2014-08-10 05:39:16 -04:00
SubSystem.py config: Add SubSystem container for simobjects 2014-08-10 05:39:16 -04:00
syscall_emul.cc syscall_emul: fix warn_once behavior 2015-05-05 09:25:59 -07:00
syscall_emul.hh syscall_emul: fix warn_once behavior 2015-05-05 09:25:59 -07:00
syscall_emul_buf.hh syscall_emul: devirtualize BaseBufferArg methods 2014-10-22 15:53:34 -07:00
syscallreturn.hh syscall_emul: add retry flag to SyscallReturn 2014-09-02 16:07:50 -05:00
system.cc sim: Don't clear the active CPU vector in System::initState 2015-05-15 13:39:44 -04:00
system.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
System.py mem: mmap the backing store with MAP_NORESERVE 2015-02-16 03:33:47 -05:00
ticked_object.cc sim: Fix checkpoint restore for Ticked 2014-09-03 07:42:25 -04:00
ticked_object.hh cpu: Probe points for basic PMU stats 2014-10-16 05:49:41 -04:00
TickedObject.py cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
voltage_domain.cc energy: Small extentions and fixes for DVFS handler 2014-06-16 14:59:44 +01:00
voltage_domain.hh energy: Tighter checking of levels for DFS systems 2014-08-12 19:00:44 +01:00
VoltageDomain.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
vptr.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00