138 lines
4.8 KiB
C++
138 lines
4.8 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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* Stephen Hines
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*/
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#include <string>
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#include "arch/arm/table_walker.hh"
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#include "arch/arm/tlb.hh"
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#include "arch/arm/vtophys.hh"
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#include "base/chunk_generator.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "mem/vport.hh"
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using namespace std;
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using namespace ArmISA;
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Addr
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ArmISA::vtophys(Addr vaddr)
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{
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fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
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}
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Addr
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ArmISA::vtophys(ThreadContext *tc, Addr addr)
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{
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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if (!sctlr.m) {
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// Translation is currently disabled PA == VA
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return addr;
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}
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bool success;
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Addr pa;
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ArmISA::TLB *tlb;
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// Check the TLBs far a translation
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// It's possible that there is a validy translation in the tlb
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// that is no loger valid in the page table in memory
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// so we need to check here first
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tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
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success = tlb->translateFunctional(tc, addr, pa);
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if (success)
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return pa;
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tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
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success = tlb->translateFunctional(tc, addr, pa);
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if (success)
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return pa;
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// We've failed everything, so we need to do a
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// hardware tlb walk without messing with any
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// state
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uint32_t N = tc->readMiscReg(MISCREG_TTBCR);
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Addr ttbr;
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if (N == 0 || !mbits(addr, 31, 32-N)) {
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ttbr = tc->readMiscReg(MISCREG_TTBR0);
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} else {
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ttbr = tc->readMiscReg(MISCREG_TTBR1);
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N = 0;
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}
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FunctionalPort *port = tc->getPhysPort();
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Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(addr,31-N,20) << 2);
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TableWalker::L1Descriptor l1desc;
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l1desc.data = port->read<uint32_t>(l1desc_addr);
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if (l1desc.type() == TableWalker::L1Descriptor::Ignore ||
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l1desc.type() == TableWalker::L1Descriptor::Reserved) {
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warn("Unable to translate virtual address: %#x\n", addr);
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return -1;
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}
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if (l1desc.type() == TableWalker::L1Descriptor::Section)
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return l1desc.paddr(addr);
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// Didn't find it at the first level, try againt
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Addr l2desc_addr = l1desc.l2Addr() | (bits(addr, 19, 12) << 2);
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TableWalker::L2Descriptor l2desc;
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l2desc.data = port->read<uint32_t>(l2desc_addr);
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if (l2desc.invalid()) {
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warn("Unable to translate virtual address: %#x\n", addr);
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return -1;
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}
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return l2desc.paddr(addr);
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}
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bool
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ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
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{
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if (vtophys(tc, vaddr) != -1)
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return true;
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return false;
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}
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