f6fc18f03d
SConscript:
easier to fix than temporarily remove
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
mem needed for both fullsys and syscall
dev/baddev.cc:
fix for new mem system
dev/io_device.cc:
fix typo
dev/io_device.hh:
PioDevice needs to be a memobject
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
fix for new mem systems
dev/platform.cc:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
rather than the platform have a pointer to pciconfig, go the other
way so all devices are the same and can have a platform pointer
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart8250.cc:
python/m5/objects/AlphaConsole.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/Device.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/System.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
fixes for newmem
--HG--
extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105
130 lines
4 KiB
C++
130 lines
4 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of top level class for the Tsunami chipset. This class just
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* retains pointers to all its children so the children can communicate.
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*/
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#ifndef __DEV_TSUNAMI_HH__
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#define __DEV_TSUNAMI_HH__
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#include "dev/platform.hh"
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class IdeController;
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class TsunamiCChip;
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class TsunamiPChip;
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class TsunamiIO;
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class System;
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/**
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* Top level class for Tsunami Chipset emulation.
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* This structure just contains pointers to all the
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* children so the children can commnicate to do the
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* read work
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*/
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class Tsunami : public Platform
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{
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public:
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/** Max number of CPUs in a Tsunami */
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static const int Max_CPUs = 64;
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/** Pointer to the system */
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System *system;
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/** Pointer to the TsunamiIO device which has the RTC */
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TsunamiIO *io;
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/** Pointer to the Tsunami CChip.
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* The chip contains some configuration information and
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* all the interrupt mask and status registers
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*/
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TsunamiCChip *cchip;
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/** Pointer to the Tsunami PChip.
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* The pchip is the interface to the PCI bus, in our case
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* it does not have to do much.
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*/
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TsunamiPChip *pchip;
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int intr_sum_type[Tsunami::Max_CPUs];
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int ipi_pending[Tsunami::Max_CPUs];
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public:
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/**
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* Constructor for the Tsunami Class.
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* @param name name of the object
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* @param intrctrl pointer to the interrupt controller
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*/
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Tsunami(const std::string &name, System *s, IntrControl *intctrl);
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/**
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* Return the interrupting frequency to AlphaAccess
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* @return frequency of RTC interrupts
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*/
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virtual Tick intrFrequency();
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/**
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* Cause the cpu to post a serial interrupt to the CPU.
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*/
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virtual void postConsoleInt();
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/**
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* Clear a posted CPU interrupt (id=55)
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*/
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virtual void clearConsoleInt();
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/**
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* Cause the chipset to post a cpi interrupt to the CPU.
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*/
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virtual void postPciInt(int line);
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/**
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* Clear a posted PCI->CPU interrupt
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*/
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virtual void clearPciInt(int line);
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virtual Addr pciToDma(Addr pciAddr) const;
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __DEV_TSUNAMI_HH__
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