425dda00df
all macros in ev5.hh to inline functions or constant typed
variables and make them follow our style while we're at it.
All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
dev/ns_gige.cc:
kern/tru64/tru64_events.cc:
deal with changes in ev5.hh
arch/alpha/ev5.hh:
Macros are nasty, so let's get rid of them. Convert all
all macros to inline functions or constant typed variables.
Make them follow our style while we're at it.
All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.
arch/alpha/isa_traits.hh:
move some of the ev5 specific code into the isa
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
deal with isa addition
cpu/exec_context.hh:
be less isa specific and use the isa traits to figure out
what we can.
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
deal with changes in ev5.hh
I don't believe this masking is actually necessary. We should
look at removing it later.
dev/ide_ctrl.cc:
sort #includes
deal with changes in ev5.hh
--HG--
extra : convert_revision : c8a3adf0a4b1d198aefe38fc38b295abf289b08a
80 lines
3.2 KiB
C++
80 lines
3.2 KiB
C++
/* $Id$ */
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#ifndef __ARCH_ALPHA_EV5_HH__
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#define __ARCH_ALPHA_EV5_HH__
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namespace EV5 {
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#ifdef ALPHA_TLASER
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const uint64_t AsnMask = ULL(0x7f);
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#else
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const uint64_t AsnMask = ULL(0xff);
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#endif
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const int VAddrImplBits = 43;
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const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
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const Addr VAddrUnImplMask = ~VAddrImplMask;
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inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
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inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; }
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inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
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inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
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inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
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#ifdef ALPHA_TLASER
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inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
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const int PAddrImplBits = 40;
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#else
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inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
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const int PAddrImplBits = 44; // for Tsunami
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#endif
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const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
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const Addr PAddrUncachedBit39 = ULL(0x8000000000);
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const Addr PAddrUncachedBit40 = ULL(0x10000000000);
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const Addr PAddrUncachedBit43 = ULL(0x80000000000);
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const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
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inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
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inline Addr DTB_PTE_PPN(uint64_t reg)
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{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
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inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
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inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
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inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
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inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
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inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
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inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
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inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
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inline Addr ITB_PTE_PPN(uint64_t reg)
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{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
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inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
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inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
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inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
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inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
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inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
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inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
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inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
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inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
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inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
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inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
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inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
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inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
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const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
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const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
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const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
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const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
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const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
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const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
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inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; }
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inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
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const Addr PalBase = 0x4000;
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const Addr PalMax = 0x10000;
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/* namespace EV5 */ }
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#endif // __ARCH_ALPHA_EV5_HH__
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