1483496803
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5) inadvertently fixed a bug in the Minor CPU model which caused it to treat software prefetches as regular loads. Prior to this changeset, Minor did an ad-hoc generation of memory commands that left out the PF check; because it now uses the common code that the other CPU models use, it generates prefetches properly. These stat changes reflect the fact that the Minor model now issues SoftPFReqs.
27 lines
1.5 KiB
Text
Executable file
27 lines
1.5 KiB
Text
Executable file
gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Mar 15 2015 20:30:55
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gem5 started Mar 15 2015 20:31:14
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gem5 executing on zizzer2
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
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Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav
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Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2
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Global frequency set at 1000000000000 ticks per second
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0: system.cpu.isa: ISA system set to: 0 0x3623b60
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info: Entering event queue @ 0. Starting simulation...
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TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
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Standard Cell Placement and Global Routing Program
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Authors: Carl Sechen, Bill Swartz
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Yale University
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info: Increasing stack size by one page.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
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31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
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46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
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61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
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76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
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91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
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106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
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122 123 124 Exiting @ tick 131756455500 because target called exit()
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