1733 lines
197 KiB
Text
1733 lines
197 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000500 # Number of seconds simulated
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sim_ticks 500337000 # Number of ticks simulated
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final_tick 500337000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_tick_rate 90464630 # Simulator tick rate (ticks/s)
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host_mem_usage 231728 # Number of bytes of host memory used
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host_seconds 5.53 # Real time elapsed on the host
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0 75919 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1 81043 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2 80577 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3 79993 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu4 82197 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu5 76405 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu6 83460 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu7 78091 # Number of bytes read from this memory
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system.physmem.bytes_read::total 637685 # Number of bytes read from this memory
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system.physmem.bytes_written::writebacks 400320 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0 5398 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1 5467 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu2 5426 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu3 5579 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu4 5520 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu5 5451 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu6 5589 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu7 5357 # Number of bytes written to this memory
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system.physmem.bytes_written::total 444107 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0 10777 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1 10924 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2 11088 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu4 11007 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu5 10948 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu6 11010 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu7 10807 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 87506 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 6255 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0 5398 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1 5467 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu2 5426 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu3 5579 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu4 5520 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu5 5451 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu6 5589 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu7 5357 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 50042 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0 151735730 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1 161976828 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2 161045455 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3 159878242 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu4 164283273 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu5 152707075 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu6 166807572 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu7 156076804 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1274510980 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 800100732 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0 10788728 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1 10926635 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu2 10844691 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu3 11150485 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu4 11032564 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu5 10894657 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu6 11170471 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu7 10706784 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 887615747 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 800100732 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0 162524459 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1 172903463 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2 171890146 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3 171028727 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu4 175315837 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu5 163601732 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu6 177978043 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu7 166783588 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2162126727 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.num_reads 99905 # number of read accesses completed
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system.cpu0.num_writes 55400 # number of write accesses completed
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system.cpu0.l1c.tags.replacements 22463 # number of replacements
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system.cpu0.l1c.tags.tagsinuse 391.153981 # Cycle average of tags in use
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system.cpu0.l1c.tags.total_refs 13877 # Total number of references to valid blocks.
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system.cpu0.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks.
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system.cpu0.l1c.tags.avg_refs 0.606990 # Average number of references to valid blocks.
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system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.l1c.tags.occ_blocks::cpu0 391.153981 # Average occupied blocks per requestor
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system.cpu0.l1c.tags.occ_percent::cpu0 0.763973 # Average percentage of cache occupancy
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system.cpu0.l1c.tags.occ_percent::total 0.763973 # Average percentage of cache occupancy
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system.cpu0.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
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system.cpu0.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id
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system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
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system.cpu0.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
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system.cpu0.l1c.tags.tag_accesses 340651 # Number of tag accesses
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system.cpu0.l1c.tags.data_accesses 340651 # Number of data accesses
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system.cpu0.l1c.ReadReq_hits::cpu0 8894 # number of ReadReq hits
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system.cpu0.l1c.ReadReq_hits::total 8894 # number of ReadReq hits
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system.cpu0.l1c.WriteReq_hits::cpu0 1261 # number of WriteReq hits
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system.cpu0.l1c.WriteReq_hits::total 1261 # number of WriteReq hits
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system.cpu0.l1c.demand_hits::cpu0 10155 # number of demand (read+write) hits
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system.cpu0.l1c.demand_hits::total 10155 # number of demand (read+write) hits
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system.cpu0.l1c.overall_hits::cpu0 10155 # number of overall hits
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system.cpu0.l1c.overall_hits::total 10155 # number of overall hits
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system.cpu0.l1c.ReadReq_misses::cpu0 36720 # number of ReadReq misses
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system.cpu0.l1c.ReadReq_misses::total 36720 # number of ReadReq misses
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system.cpu0.l1c.WriteReq_misses::cpu0 24041 # number of WriteReq misses
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system.cpu0.l1c.WriteReq_misses::total 24041 # number of WriteReq misses
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system.cpu0.l1c.demand_misses::cpu0 60761 # number of demand (read+write) misses
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system.cpu0.l1c.demand_misses::total 60761 # number of demand (read+write) misses
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system.cpu0.l1c.overall_misses::cpu0 60761 # number of overall misses
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system.cpu0.l1c.overall_misses::total 60761 # number of overall misses
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system.cpu0.l1c.ReadReq_miss_latency::cpu0 677337671 # number of ReadReq miss cycles
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system.cpu0.l1c.ReadReq_miss_latency::total 677337671 # number of ReadReq miss cycles
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system.cpu0.l1c.WriteReq_miss_latency::cpu0 564207136 # number of WriteReq miss cycles
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system.cpu0.l1c.WriteReq_miss_latency::total 564207136 # number of WriteReq miss cycles
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system.cpu0.l1c.demand_miss_latency::cpu0 1241544807 # number of demand (read+write) miss cycles
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system.cpu0.l1c.demand_miss_latency::total 1241544807 # number of demand (read+write) miss cycles
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system.cpu0.l1c.overall_miss_latency::cpu0 1241544807 # number of overall miss cycles
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system.cpu0.l1c.overall_miss_latency::total 1241544807 # number of overall miss cycles
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system.cpu0.l1c.ReadReq_accesses::cpu0 45614 # number of ReadReq accesses(hits+misses)
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system.cpu0.l1c.ReadReq_accesses::total 45614 # number of ReadReq accesses(hits+misses)
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system.cpu0.l1c.WriteReq_accesses::cpu0 25302 # number of WriteReq accesses(hits+misses)
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system.cpu0.l1c.WriteReq_accesses::total 25302 # number of WriteReq accesses(hits+misses)
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system.cpu0.l1c.demand_accesses::cpu0 70916 # number of demand (read+write) accesses
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system.cpu0.l1c.demand_accesses::total 70916 # number of demand (read+write) accesses
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system.cpu0.l1c.overall_accesses::cpu0 70916 # number of overall (read+write) accesses
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system.cpu0.l1c.overall_accesses::total 70916 # number of overall (read+write) accesses
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system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805016 # miss rate for ReadReq accesses
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system.cpu0.l1c.ReadReq_miss_rate::total 0.805016 # miss rate for ReadReq accesses
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system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.950162 # miss rate for WriteReq accesses
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system.cpu0.l1c.WriteReq_miss_rate::total 0.950162 # miss rate for WriteReq accesses
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system.cpu0.l1c.demand_miss_rate::cpu0 0.856802 # miss rate for demand accesses
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system.cpu0.l1c.demand_miss_rate::total 0.856802 # miss rate for demand accesses
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system.cpu0.l1c.overall_miss_rate::cpu0 0.856802 # miss rate for overall accesses
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system.cpu0.l1c.overall_miss_rate::total 0.856802 # miss rate for overall accesses
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system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18446.015005 # average ReadReq miss latency
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system.cpu0.l1c.ReadReq_avg_miss_latency::total 18446.015005 # average ReadReq miss latency
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system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23468.538580 # average WriteReq miss latency
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system.cpu0.l1c.WriteReq_avg_miss_latency::total 23468.538580 # average WriteReq miss latency
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system.cpu0.l1c.demand_avg_miss_latency::cpu0 20433.251708 # average overall miss latency
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system.cpu0.l1c.demand_avg_miss_latency::total 20433.251708 # average overall miss latency
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system.cpu0.l1c.overall_avg_miss_latency::cpu0 20433.251708 # average overall miss latency
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system.cpu0.l1c.overall_avg_miss_latency::total 20433.251708 # average overall miss latency
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system.cpu0.l1c.blocked_cycles::no_mshrs 800862 # number of cycles access was blocked
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system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.l1c.blocked::no_mshrs 65942 # number of cycles access was blocked
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system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.144946 # average number of cycles each access was blocked
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system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.l1c.writebacks::writebacks 10055 # number of writebacks
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system.cpu0.l1c.writebacks::total 10055 # number of writebacks
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system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36720 # number of ReadReq MSHR misses
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system.cpu0.l1c.ReadReq_mshr_misses::total 36720 # number of ReadReq MSHR misses
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system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24041 # number of WriteReq MSHR misses
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|
system.cpu0.l1c.WriteReq_mshr_misses::total 24041 # number of WriteReq MSHR misses
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|
system.cpu0.l1c.demand_mshr_misses::cpu0 60761 # number of demand (read+write) MSHR misses
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system.cpu0.l1c.demand_mshr_misses::total 60761 # number of demand (read+write) MSHR misses
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system.cpu0.l1c.overall_mshr_misses::cpu0 60761 # number of overall MSHR misses
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system.cpu0.l1c.overall_mshr_misses::total 60761 # number of overall MSHR misses
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system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9743 # number of ReadReq MSHR uncacheable
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system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable
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system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5400 # number of WriteReq MSHR uncacheable
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system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5400 # number of WriteReq MSHR uncacheable
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system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15143 # number of overall MSHR uncacheable misses
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system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15143 # number of overall MSHR uncacheable misses
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system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 640619671 # number of ReadReq MSHR miss cycles
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system.cpu0.l1c.ReadReq_mshr_miss_latency::total 640619671 # number of ReadReq MSHR miss cycles
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system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 540167136 # number of WriteReq MSHR miss cycles
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system.cpu0.l1c.WriteReq_mshr_miss_latency::total 540167136 # number of WriteReq MSHR miss cycles
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system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1180786807 # number of demand (read+write) MSHR miss cycles
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system.cpu0.l1c.demand_mshr_miss_latency::total 1180786807 # number of demand (read+write) MSHR miss cycles
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system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1180786807 # number of overall MSHR miss cycles
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system.cpu0.l1c.overall_mshr_miss_latency::total 1180786807 # number of overall MSHR miss cycles
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system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 730760811 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 730760811 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 730760811 # number of overall MSHR uncacheable cycles
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system.cpu0.l1c.overall_mshr_uncacheable_latency::total 730760811 # number of overall MSHR uncacheable cycles
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system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805016 # mshr miss rate for ReadReq accesses
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system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805016 # mshr miss rate for ReadReq accesses
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system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.950162 # mshr miss rate for WriteReq accesses
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system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.950162 # mshr miss rate for WriteReq accesses
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system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.856802 # mshr miss rate for demand accesses
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system.cpu0.l1c.demand_mshr_miss_rate::total 0.856802 # mshr miss rate for demand accesses
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system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.856802 # mshr miss rate for overall accesses
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system.cpu0.l1c.overall_mshr_miss_rate::total 0.856802 # mshr miss rate for overall accesses
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system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17446.069472 # average ReadReq mshr miss latency
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system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17446.069472 # average ReadReq mshr miss latency
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system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22468.580176 # average WriteReq mshr miss latency
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|
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22468.580176 # average WriteReq mshr miss latency
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|
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19433.301081 # average overall mshr miss latency
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|
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19433.301081 # average overall mshr miss latency
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|
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19433.301081 # average overall mshr miss latency
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|
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19433.301081 # average overall mshr miss latency
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system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75003.675562 # average ReadReq mshr uncacheable latency
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system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.675562 # average ReadReq mshr uncacheable latency
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system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 48257.334148 # average overall mshr uncacheable latency
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system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 48257.334148 # average overall mshr uncacheable latency
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system.cpu1.num_reads 99552 # number of read accesses completed
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|
system.cpu1.num_writes 55243 # number of write accesses completed
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|
system.cpu1.l1c.tags.replacements 22440 # number of replacements
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|
system.cpu1.l1c.tags.tagsinuse 392.475962 # Cycle average of tags in use
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|
system.cpu1.l1c.tags.total_refs 13641 # Total number of references to valid blocks.
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|
system.cpu1.l1c.tags.sampled_refs 22851 # Sample count of references to valid blocks.
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|
system.cpu1.l1c.tags.avg_refs 0.596954 # Average number of references to valid blocks.
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|
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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|
system.cpu1.l1c.tags.occ_blocks::cpu1 392.475962 # Average occupied blocks per requestor
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|
system.cpu1.l1c.tags.occ_percent::cpu1 0.766555 # Average percentage of cache occupancy
|
|
system.cpu1.l1c.tags.occ_percent::total 0.766555 # Average percentage of cache occupancy
|
|
system.cpu1.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id
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|
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id
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|
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
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|
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id
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|
system.cpu1.l1c.tags.tag_accesses 339640 # Number of tag accesses
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|
system.cpu1.l1c.tags.data_accesses 339640 # Number of data accesses
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|
system.cpu1.l1c.ReadReq_hits::cpu1 8906 # number of ReadReq hits
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|
system.cpu1.l1c.ReadReq_hits::total 8906 # number of ReadReq hits
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|
system.cpu1.l1c.WriteReq_hits::cpu1 1136 # number of WriteReq hits
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|
system.cpu1.l1c.WriteReq_hits::total 1136 # number of WriteReq hits
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|
system.cpu1.l1c.demand_hits::cpu1 10042 # number of demand (read+write) hits
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|
system.cpu1.l1c.demand_hits::total 10042 # number of demand (read+write) hits
|
|
system.cpu1.l1c.overall_hits::cpu1 10042 # number of overall hits
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|
system.cpu1.l1c.overall_hits::total 10042 # number of overall hits
|
|
system.cpu1.l1c.ReadReq_misses::cpu1 36595 # number of ReadReq misses
|
|
system.cpu1.l1c.ReadReq_misses::total 36595 # number of ReadReq misses
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|
system.cpu1.l1c.WriteReq_misses::cpu1 24033 # number of WriteReq misses
|
|
system.cpu1.l1c.WriteReq_misses::total 24033 # number of WriteReq misses
|
|
system.cpu1.l1c.demand_misses::cpu1 60628 # number of demand (read+write) misses
|
|
system.cpu1.l1c.demand_misses::total 60628 # number of demand (read+write) misses
|
|
system.cpu1.l1c.overall_misses::cpu1 60628 # number of overall misses
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|
system.cpu1.l1c.overall_misses::total 60628 # number of overall misses
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|
system.cpu1.l1c.ReadReq_miss_latency::cpu1 675076804 # number of ReadReq miss cycles
|
|
system.cpu1.l1c.ReadReq_miss_latency::total 675076804 # number of ReadReq miss cycles
|
|
system.cpu1.l1c.WriteReq_miss_latency::cpu1 561344066 # number of WriteReq miss cycles
|
|
system.cpu1.l1c.WriteReq_miss_latency::total 561344066 # number of WriteReq miss cycles
|
|
system.cpu1.l1c.demand_miss_latency::cpu1 1236420870 # number of demand (read+write) miss cycles
|
|
system.cpu1.l1c.demand_miss_latency::total 1236420870 # number of demand (read+write) miss cycles
|
|
system.cpu1.l1c.overall_miss_latency::cpu1 1236420870 # number of overall miss cycles
|
|
system.cpu1.l1c.overall_miss_latency::total 1236420870 # number of overall miss cycles
|
|
system.cpu1.l1c.ReadReq_accesses::cpu1 45501 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l1c.ReadReq_accesses::total 45501 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l1c.WriteReq_accesses::cpu1 25169 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.l1c.demand_accesses::cpu1 70670 # number of demand (read+write) accesses
|
|
system.cpu1.l1c.demand_accesses::total 70670 # number of demand (read+write) accesses
|
|
system.cpu1.l1c.overall_accesses::cpu1 70670 # number of overall (read+write) accesses
|
|
system.cpu1.l1c.overall_accesses::total 70670 # number of overall (read+write) accesses
|
|
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804268 # miss rate for ReadReq accesses
|
|
system.cpu1.l1c.ReadReq_miss_rate::total 0.804268 # miss rate for ReadReq accesses
|
|
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954865 # miss rate for WriteReq accesses
|
|
system.cpu1.l1c.WriteReq_miss_rate::total 0.954865 # miss rate for WriteReq accesses
|
|
system.cpu1.l1c.demand_miss_rate::cpu1 0.857903 # miss rate for demand accesses
|
|
system.cpu1.l1c.demand_miss_rate::total 0.857903 # miss rate for demand accesses
|
|
system.cpu1.l1c.overall_miss_rate::cpu1 0.857903 # miss rate for overall accesses
|
|
system.cpu1.l1c.overall_miss_rate::total 0.857903 # miss rate for overall accesses
|
|
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18447.241536 # average ReadReq miss latency
|
|
system.cpu1.l1c.ReadReq_avg_miss_latency::total 18447.241536 # average ReadReq miss latency
|
|
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23357.219906 # average WriteReq miss latency
|
|
system.cpu1.l1c.WriteReq_avg_miss_latency::total 23357.219906 # average WriteReq miss latency
|
|
system.cpu1.l1c.demand_avg_miss_latency::cpu1 20393.561886 # average overall miss latency
|
|
system.cpu1.l1c.demand_avg_miss_latency::total 20393.561886 # average overall miss latency
|
|
system.cpu1.l1c.overall_avg_miss_latency::cpu1 20393.561886 # average overall miss latency
|
|
system.cpu1.l1c.overall_avg_miss_latency::total 20393.561886 # average overall miss latency
|
|
system.cpu1.l1c.blocked_cycles::no_mshrs 800224 # number of cycles access was blocked
|
|
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l1c.blocked::no_mshrs 65844 # number of cycles access was blocked
|
|
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.153332 # average number of cycles each access was blocked
|
|
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.l1c.writebacks::writebacks 9864 # number of writebacks
|
|
system.cpu1.l1c.writebacks::total 9864 # number of writebacks
|
|
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36595 # number of ReadReq MSHR misses
|
|
system.cpu1.l1c.ReadReq_mshr_misses::total 36595 # number of ReadReq MSHR misses
|
|
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24033 # number of WriteReq MSHR misses
|
|
system.cpu1.l1c.WriteReq_mshr_misses::total 24033 # number of WriteReq MSHR misses
|
|
system.cpu1.l1c.demand_mshr_misses::cpu1 60628 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l1c.demand_mshr_misses::total 60628 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l1c.overall_mshr_misses::cpu1 60628 # number of overall MSHR misses
|
|
system.cpu1.l1c.overall_mshr_misses::total 60628 # number of overall MSHR misses
|
|
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9811 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9811 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5468 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5468 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15279 # number of overall MSHR uncacheable misses
|
|
system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15279 # number of overall MSHR uncacheable misses
|
|
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 638481804 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 638481804 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 537312066 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 537312066 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1175793870 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l1c.demand_mshr_miss_latency::total 1175793870 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1175793870 # number of overall MSHR miss cycles
|
|
system.cpu1.l1c.overall_mshr_miss_latency::total 1175793870 # number of overall MSHR miss cycles
|
|
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 734637731 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 734637731 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 734637731 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 734637731 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804268 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804268 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954865 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954865 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857903 # mshr miss rate for demand accesses
|
|
system.cpu1.l1c.demand_mshr_miss_rate::total 0.857903 # mshr miss rate for demand accesses
|
|
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857903 # mshr miss rate for overall accesses
|
|
system.cpu1.l1c.overall_mshr_miss_rate::total 0.857903 # mshr miss rate for overall accesses
|
|
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17447.241536 # average ReadReq mshr miss latency
|
|
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17447.241536 # average ReadReq mshr miss latency
|
|
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22357.261515 # average WriteReq mshr miss latency
|
|
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22357.261515 # average WriteReq mshr miss latency
|
|
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19393.578380 # average overall mshr miss latency
|
|
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19393.578380 # average overall mshr miss latency
|
|
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19393.578380 # average overall mshr miss latency
|
|
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19393.578380 # average overall mshr miss latency
|
|
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74878.985934 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74878.985934 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48081.532234 # average overall mshr uncacheable latency
|
|
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48081.532234 # average overall mshr uncacheable latency
|
|
system.cpu2.num_reads 100001 # number of read accesses completed
|
|
system.cpu2.num_writes 55556 # number of write accesses completed
|
|
system.cpu2.l1c.tags.replacements 22129 # number of replacements
|
|
system.cpu2.l1c.tags.tagsinuse 390.469202 # Cycle average of tags in use
|
|
system.cpu2.l1c.tags.total_refs 13617 # Total number of references to valid blocks.
|
|
system.cpu2.l1c.tags.sampled_refs 22527 # Sample count of references to valid blocks.
|
|
system.cpu2.l1c.tags.avg_refs 0.604475 # Average number of references to valid blocks.
|
|
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.l1c.tags.occ_blocks::cpu2 390.469202 # Average occupied blocks per requestor
|
|
system.cpu2.l1c.tags.occ_percent::cpu2 0.762635 # Average percentage of cache occupancy
|
|
system.cpu2.l1c.tags.occ_percent::total 0.762635 # Average percentage of cache occupancy
|
|
system.cpu2.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
|
|
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id
|
|
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
|
|
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
|
|
system.cpu2.l1c.tags.tag_accesses 339163 # Number of tag accesses
|
|
system.cpu2.l1c.tags.data_accesses 339163 # Number of data accesses
|
|
system.cpu2.l1c.ReadReq_hits::cpu2 8741 # number of ReadReq hits
|
|
system.cpu2.l1c.ReadReq_hits::total 8741 # number of ReadReq hits
|
|
system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits
|
|
system.cpu2.l1c.WriteReq_hits::total 1177 # number of WriteReq hits
|
|
system.cpu2.l1c.demand_hits::cpu2 9918 # number of demand (read+write) hits
|
|
system.cpu2.l1c.demand_hits::total 9918 # number of demand (read+write) hits
|
|
system.cpu2.l1c.overall_hits::cpu2 9918 # number of overall hits
|
|
system.cpu2.l1c.overall_hits::total 9918 # number of overall hits
|
|
system.cpu2.l1c.ReadReq_misses::cpu2 36520 # number of ReadReq misses
|
|
system.cpu2.l1c.ReadReq_misses::total 36520 # number of ReadReq misses
|
|
system.cpu2.l1c.WriteReq_misses::cpu2 24129 # number of WriteReq misses
|
|
system.cpu2.l1c.WriteReq_misses::total 24129 # number of WriteReq misses
|
|
system.cpu2.l1c.demand_misses::cpu2 60649 # number of demand (read+write) misses
|
|
system.cpu2.l1c.demand_misses::total 60649 # number of demand (read+write) misses
|
|
system.cpu2.l1c.overall_misses::cpu2 60649 # number of overall misses
|
|
system.cpu2.l1c.overall_misses::total 60649 # number of overall misses
|
|
system.cpu2.l1c.ReadReq_miss_latency::cpu2 666978729 # number of ReadReq miss cycles
|
|
system.cpu2.l1c.ReadReq_miss_latency::total 666978729 # number of ReadReq miss cycles
|
|
system.cpu2.l1c.WriteReq_miss_latency::cpu2 561823462 # number of WriteReq miss cycles
|
|
system.cpu2.l1c.WriteReq_miss_latency::total 561823462 # number of WriteReq miss cycles
|
|
system.cpu2.l1c.demand_miss_latency::cpu2 1228802191 # number of demand (read+write) miss cycles
|
|
system.cpu2.l1c.demand_miss_latency::total 1228802191 # number of demand (read+write) miss cycles
|
|
system.cpu2.l1c.overall_miss_latency::cpu2 1228802191 # number of overall miss cycles
|
|
system.cpu2.l1c.overall_miss_latency::total 1228802191 # number of overall miss cycles
|
|
system.cpu2.l1c.ReadReq_accesses::cpu2 45261 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.l1c.ReadReq_accesses::total 45261 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.l1c.WriteReq_accesses::cpu2 25306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.l1c.WriteReq_accesses::total 25306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.l1c.demand_accesses::cpu2 70567 # number of demand (read+write) accesses
|
|
system.cpu2.l1c.demand_accesses::total 70567 # number of demand (read+write) accesses
|
|
system.cpu2.l1c.overall_accesses::cpu2 70567 # number of overall (read+write) accesses
|
|
system.cpu2.l1c.overall_accesses::total 70567 # number of overall (read+write) accesses
|
|
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806876 # miss rate for ReadReq accesses
|
|
system.cpu2.l1c.ReadReq_miss_rate::total 0.806876 # miss rate for ReadReq accesses
|
|
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953489 # miss rate for WriteReq accesses
|
|
system.cpu2.l1c.WriteReq_miss_rate::total 0.953489 # miss rate for WriteReq accesses
|
|
system.cpu2.l1c.demand_miss_rate::cpu2 0.859453 # miss rate for demand accesses
|
|
system.cpu2.l1c.demand_miss_rate::total 0.859453 # miss rate for demand accesses
|
|
system.cpu2.l1c.overall_miss_rate::cpu2 0.859453 # miss rate for overall accesses
|
|
system.cpu2.l1c.overall_miss_rate::total 0.859453 # miss rate for overall accesses
|
|
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18263.382503 # average ReadReq miss latency
|
|
system.cpu2.l1c.ReadReq_avg_miss_latency::total 18263.382503 # average ReadReq miss latency
|
|
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23284.158564 # average WriteReq miss latency
|
|
system.cpu2.l1c.WriteReq_avg_miss_latency::total 23284.158564 # average WriteReq miss latency
|
|
system.cpu2.l1c.demand_avg_miss_latency::cpu2 20260.881317 # average overall miss latency
|
|
system.cpu2.l1c.demand_avg_miss_latency::total 20260.881317 # average overall miss latency
|
|
system.cpu2.l1c.overall_avg_miss_latency::cpu2 20260.881317 # average overall miss latency
|
|
system.cpu2.l1c.overall_avg_miss_latency::total 20260.881317 # average overall miss latency
|
|
system.cpu2.l1c.blocked_cycles::no_mshrs 804972 # number of cycles access was blocked
|
|
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.l1c.blocked::no_mshrs 66283 # number of cycles access was blocked
|
|
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.144471 # average number of cycles each access was blocked
|
|
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.l1c.writebacks::writebacks 9821 # number of writebacks
|
|
system.cpu2.l1c.writebacks::total 9821 # number of writebacks
|
|
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36520 # number of ReadReq MSHR misses
|
|
system.cpu2.l1c.ReadReq_mshr_misses::total 36520 # number of ReadReq MSHR misses
|
|
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24129 # number of WriteReq MSHR misses
|
|
system.cpu2.l1c.WriteReq_mshr_misses::total 24129 # number of WriteReq MSHR misses
|
|
system.cpu2.l1c.demand_mshr_misses::cpu2 60649 # number of demand (read+write) MSHR misses
|
|
system.cpu2.l1c.demand_mshr_misses::total 60649 # number of demand (read+write) MSHR misses
|
|
system.cpu2.l1c.overall_mshr_misses::cpu2 60649 # number of overall MSHR misses
|
|
system.cpu2.l1c.overall_mshr_misses::total 60649 # number of overall MSHR misses
|
|
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9985 # number of ReadReq MSHR uncacheable
|
|
system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9985 # number of ReadReq MSHR uncacheable
|
|
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5427 # number of WriteReq MSHR uncacheable
|
|
system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5427 # number of WriteReq MSHR uncacheable
|
|
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15412 # number of overall MSHR uncacheable misses
|
|
system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15412 # number of overall MSHR uncacheable misses
|
|
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 630459729 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 630459729 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 537696462 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 537696462 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1168156191 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.l1c.demand_mshr_miss_latency::total 1168156191 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1168156191 # number of overall MSHR miss cycles
|
|
system.cpu2.l1c.overall_mshr_miss_latency::total 1168156191 # number of overall MSHR miss cycles
|
|
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 746431095 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 746431095 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 746431095 # number of overall MSHR uncacheable cycles
|
|
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 746431095 # number of overall MSHR uncacheable cycles
|
|
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806876 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806876 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953489 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953489 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859453 # mshr miss rate for demand accesses
|
|
system.cpu2.l1c.demand_mshr_miss_rate::total 0.859453 # mshr miss rate for demand accesses
|
|
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859453 # mshr miss rate for overall accesses
|
|
system.cpu2.l1c.overall_mshr_miss_rate::total 0.859453 # mshr miss rate for overall accesses
|
|
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17263.409885 # average ReadReq mshr miss latency
|
|
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17263.409885 # average ReadReq mshr miss latency
|
|
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22284.241452 # average WriteReq mshr miss latency
|
|
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22284.241452 # average WriteReq mshr miss latency
|
|
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19260.930782 # average overall mshr miss latency
|
|
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19260.930782 # average overall mshr miss latency
|
|
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19260.930782 # average overall mshr miss latency
|
|
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19260.930782 # average overall mshr miss latency
|
|
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 74755.242364 # average ReadReq mshr uncacheable latency
|
|
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74755.242364 # average ReadReq mshr uncacheable latency
|
|
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 48431.812549 # average overall mshr uncacheable latency
|
|
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 48431.812549 # average overall mshr uncacheable latency
|
|
system.cpu3.num_reads 99831 # number of read accesses completed
|
|
system.cpu3.num_writes 55461 # number of write accesses completed
|
|
system.cpu3.l1c.tags.replacements 22291 # number of replacements
|
|
system.cpu3.l1c.tags.tagsinuse 391.006782 # Cycle average of tags in use
|
|
system.cpu3.l1c.tags.total_refs 13350 # Total number of references to valid blocks.
|
|
system.cpu3.l1c.tags.sampled_refs 22681 # Sample count of references to valid blocks.
|
|
system.cpu3.l1c.tags.avg_refs 0.588598 # Average number of references to valid blocks.
|
|
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.l1c.tags.occ_blocks::cpu3 391.006782 # Average occupied blocks per requestor
|
|
system.cpu3.l1c.tags.occ_percent::cpu3 0.763685 # Average percentage of cache occupancy
|
|
system.cpu3.l1c.tags.occ_percent::total 0.763685 # Average percentage of cache occupancy
|
|
system.cpu3.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id
|
|
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id
|
|
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
|
|
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id
|
|
system.cpu3.l1c.tags.tag_accesses 338050 # Number of tag accesses
|
|
system.cpu3.l1c.tags.data_accesses 338050 # Number of data accesses
|
|
system.cpu3.l1c.ReadReq_hits::cpu3 8529 # number of ReadReq hits
|
|
system.cpu3.l1c.ReadReq_hits::total 8529 # number of ReadReq hits
|
|
system.cpu3.l1c.WriteReq_hits::cpu3 1176 # number of WriteReq hits
|
|
system.cpu3.l1c.WriteReq_hits::total 1176 # number of WriteReq hits
|
|
system.cpu3.l1c.demand_hits::cpu3 9705 # number of demand (read+write) hits
|
|
system.cpu3.l1c.demand_hits::total 9705 # number of demand (read+write) hits
|
|
system.cpu3.l1c.overall_hits::cpu3 9705 # number of overall hits
|
|
system.cpu3.l1c.overall_hits::total 9705 # number of overall hits
|
|
system.cpu3.l1c.ReadReq_misses::cpu3 36689 # number of ReadReq misses
|
|
system.cpu3.l1c.ReadReq_misses::total 36689 # number of ReadReq misses
|
|
system.cpu3.l1c.WriteReq_misses::cpu3 23899 # number of WriteReq misses
|
|
system.cpu3.l1c.WriteReq_misses::total 23899 # number of WriteReq misses
|
|
system.cpu3.l1c.demand_misses::cpu3 60588 # number of demand (read+write) misses
|
|
system.cpu3.l1c.demand_misses::total 60588 # number of demand (read+write) misses
|
|
system.cpu3.l1c.overall_misses::cpu3 60588 # number of overall misses
|
|
system.cpu3.l1c.overall_misses::total 60588 # number of overall misses
|
|
system.cpu3.l1c.ReadReq_miss_latency::cpu3 675943664 # number of ReadReq miss cycles
|
|
system.cpu3.l1c.ReadReq_miss_latency::total 675943664 # number of ReadReq miss cycles
|
|
system.cpu3.l1c.WriteReq_miss_latency::cpu3 557387689 # number of WriteReq miss cycles
|
|
system.cpu3.l1c.WriteReq_miss_latency::total 557387689 # number of WriteReq miss cycles
|
|
system.cpu3.l1c.demand_miss_latency::cpu3 1233331353 # number of demand (read+write) miss cycles
|
|
system.cpu3.l1c.demand_miss_latency::total 1233331353 # number of demand (read+write) miss cycles
|
|
system.cpu3.l1c.overall_miss_latency::cpu3 1233331353 # number of overall miss cycles
|
|
system.cpu3.l1c.overall_miss_latency::total 1233331353 # number of overall miss cycles
|
|
system.cpu3.l1c.ReadReq_accesses::cpu3 45218 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.l1c.ReadReq_accesses::total 45218 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.l1c.WriteReq_accesses::cpu3 25075 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.l1c.WriteReq_accesses::total 25075 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.l1c.demand_accesses::cpu3 70293 # number of demand (read+write) accesses
|
|
system.cpu3.l1c.demand_accesses::total 70293 # number of demand (read+write) accesses
|
|
system.cpu3.l1c.overall_accesses::cpu3 70293 # number of overall (read+write) accesses
|
|
system.cpu3.l1c.overall_accesses::total 70293 # number of overall (read+write) accesses
|
|
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811380 # miss rate for ReadReq accesses
|
|
system.cpu3.l1c.ReadReq_miss_rate::total 0.811380 # miss rate for ReadReq accesses
|
|
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953101 # miss rate for WriteReq accesses
|
|
system.cpu3.l1c.WriteReq_miss_rate::total 0.953101 # miss rate for WriteReq accesses
|
|
system.cpu3.l1c.demand_miss_rate::cpu3 0.861935 # miss rate for demand accesses
|
|
system.cpu3.l1c.demand_miss_rate::total 0.861935 # miss rate for demand accesses
|
|
system.cpu3.l1c.overall_miss_rate::cpu3 0.861935 # miss rate for overall accesses
|
|
system.cpu3.l1c.overall_miss_rate::total 0.861935 # miss rate for overall accesses
|
|
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18423.605549 # average ReadReq miss latency
|
|
system.cpu3.l1c.ReadReq_avg_miss_latency::total 18423.605549 # average ReadReq miss latency
|
|
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23322.636470 # average WriteReq miss latency
|
|
system.cpu3.l1c.WriteReq_avg_miss_latency::total 23322.636470 # average WriteReq miss latency
|
|
system.cpu3.l1c.demand_avg_miss_latency::cpu3 20356.033422 # average overall miss latency
|
|
system.cpu3.l1c.demand_avg_miss_latency::total 20356.033422 # average overall miss latency
|
|
system.cpu3.l1c.overall_avg_miss_latency::cpu3 20356.033422 # average overall miss latency
|
|
system.cpu3.l1c.overall_avg_miss_latency::total 20356.033422 # average overall miss latency
|
|
system.cpu3.l1c.blocked_cycles::no_mshrs 801051 # number of cycles access was blocked
|
|
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.l1c.blocked::no_mshrs 65873 # number of cycles access was blocked
|
|
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.160536 # average number of cycles each access was blocked
|
|
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.l1c.writebacks::writebacks 9857 # number of writebacks
|
|
system.cpu3.l1c.writebacks::total 9857 # number of writebacks
|
|
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36689 # number of ReadReq MSHR misses
|
|
system.cpu3.l1c.ReadReq_mshr_misses::total 36689 # number of ReadReq MSHR misses
|
|
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23899 # number of WriteReq MSHR misses
|
|
system.cpu3.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses
|
|
system.cpu3.l1c.demand_mshr_misses::cpu3 60588 # number of demand (read+write) MSHR misses
|
|
system.cpu3.l1c.demand_mshr_misses::total 60588 # number of demand (read+write) MSHR misses
|
|
system.cpu3.l1c.overall_mshr_misses::cpu3 60588 # number of overall MSHR misses
|
|
system.cpu3.l1c.overall_mshr_misses::total 60588 # number of overall MSHR misses
|
|
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9849 # number of ReadReq MSHR uncacheable
|
|
system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9849 # number of ReadReq MSHR uncacheable
|
|
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5582 # number of WriteReq MSHR uncacheable
|
|
system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5582 # number of WriteReq MSHR uncacheable
|
|
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15431 # number of overall MSHR uncacheable misses
|
|
system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15431 # number of overall MSHR uncacheable misses
|
|
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 639257664 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 639257664 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 533488689 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 533488689 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1172746353 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.l1c.demand_mshr_miss_latency::total 1172746353 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1172746353 # number of overall MSHR miss cycles
|
|
system.cpu3.l1c.overall_mshr_miss_latency::total 1172746353 # number of overall MSHR miss cycles
|
|
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 738856089 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 738856089 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 738856089 # number of overall MSHR uncacheable cycles
|
|
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 738856089 # number of overall MSHR uncacheable cycles
|
|
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811380 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811380 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953101 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953101 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861935 # mshr miss rate for demand accesses
|
|
system.cpu3.l1c.demand_mshr_miss_rate::total 0.861935 # mshr miss rate for demand accesses
|
|
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861935 # mshr miss rate for overall accesses
|
|
system.cpu3.l1c.overall_mshr_miss_rate::total 0.861935 # mshr miss rate for overall accesses
|
|
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17423.687318 # average ReadReq mshr miss latency
|
|
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17423.687318 # average ReadReq mshr miss latency
|
|
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22322.636470 # average WriteReq mshr miss latency
|
|
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22322.636470 # average WriteReq mshr miss latency
|
|
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19356.082937 # average overall mshr miss latency
|
|
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19356.082937 # average overall mshr miss latency
|
|
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19356.082937 # average overall mshr miss latency
|
|
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19356.082937 # average overall mshr miss latency
|
|
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75018.386537 # average ReadReq mshr uncacheable latency
|
|
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75018.386537 # average ReadReq mshr uncacheable latency
|
|
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 47881.283715 # average overall mshr uncacheable latency
|
|
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 47881.283715 # average overall mshr uncacheable latency
|
|
system.cpu4.num_reads 99911 # number of read accesses completed
|
|
system.cpu4.num_writes 55300 # number of write accesses completed
|
|
system.cpu4.l1c.tags.replacements 22364 # number of replacements
|
|
system.cpu4.l1c.tags.tagsinuse 391.705900 # Cycle average of tags in use
|
|
system.cpu4.l1c.tags.total_refs 13535 # Total number of references to valid blocks.
|
|
system.cpu4.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks.
|
|
system.cpu4.l1c.tags.avg_refs 0.594344 # Average number of references to valid blocks.
|
|
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu4.l1c.tags.occ_blocks::cpu4 391.705900 # Average occupied blocks per requestor
|
|
system.cpu4.l1c.tags.occ_percent::cpu4 0.765051 # Average percentage of cache occupancy
|
|
system.cpu4.l1c.tags.occ_percent::total 0.765051 # Average percentage of cache occupancy
|
|
system.cpu4.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id
|
|
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id
|
|
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
|
|
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id
|
|
system.cpu4.l1c.tags.tag_accesses 339861 # Number of tag accesses
|
|
system.cpu4.l1c.tags.data_accesses 339861 # Number of data accesses
|
|
system.cpu4.l1c.ReadReq_hits::cpu4 8886 # number of ReadReq hits
|
|
system.cpu4.l1c.ReadReq_hits::total 8886 # number of ReadReq hits
|
|
system.cpu4.l1c.WriteReq_hits::cpu4 1168 # number of WriteReq hits
|
|
system.cpu4.l1c.WriteReq_hits::total 1168 # number of WriteReq hits
|
|
system.cpu4.l1c.demand_hits::cpu4 10054 # number of demand (read+write) hits
|
|
system.cpu4.l1c.demand_hits::total 10054 # number of demand (read+write) hits
|
|
system.cpu4.l1c.overall_hits::cpu4 10054 # number of overall hits
|
|
system.cpu4.l1c.overall_hits::total 10054 # number of overall hits
|
|
system.cpu4.l1c.ReadReq_misses::cpu4 36446 # number of ReadReq misses
|
|
system.cpu4.l1c.ReadReq_misses::total 36446 # number of ReadReq misses
|
|
system.cpu4.l1c.WriteReq_misses::cpu4 24191 # number of WriteReq misses
|
|
system.cpu4.l1c.WriteReq_misses::total 24191 # number of WriteReq misses
|
|
system.cpu4.l1c.demand_misses::cpu4 60637 # number of demand (read+write) misses
|
|
system.cpu4.l1c.demand_misses::total 60637 # number of demand (read+write) misses
|
|
system.cpu4.l1c.overall_misses::cpu4 60637 # number of overall misses
|
|
system.cpu4.l1c.overall_misses::total 60637 # number of overall misses
|
|
system.cpu4.l1c.ReadReq_miss_latency::cpu4 672672441 # number of ReadReq miss cycles
|
|
system.cpu4.l1c.ReadReq_miss_latency::total 672672441 # number of ReadReq miss cycles
|
|
system.cpu4.l1c.WriteReq_miss_latency::cpu4 560233927 # number of WriteReq miss cycles
|
|
system.cpu4.l1c.WriteReq_miss_latency::total 560233927 # number of WriteReq miss cycles
|
|
system.cpu4.l1c.demand_miss_latency::cpu4 1232906368 # number of demand (read+write) miss cycles
|
|
system.cpu4.l1c.demand_miss_latency::total 1232906368 # number of demand (read+write) miss cycles
|
|
system.cpu4.l1c.overall_miss_latency::cpu4 1232906368 # number of overall miss cycles
|
|
system.cpu4.l1c.overall_miss_latency::total 1232906368 # number of overall miss cycles
|
|
system.cpu4.l1c.ReadReq_accesses::cpu4 45332 # number of ReadReq accesses(hits+misses)
|
|
system.cpu4.l1c.ReadReq_accesses::total 45332 # number of ReadReq accesses(hits+misses)
|
|
system.cpu4.l1c.WriteReq_accesses::cpu4 25359 # number of WriteReq accesses(hits+misses)
|
|
system.cpu4.l1c.WriteReq_accesses::total 25359 # number of WriteReq accesses(hits+misses)
|
|
system.cpu4.l1c.demand_accesses::cpu4 70691 # number of demand (read+write) accesses
|
|
system.cpu4.l1c.demand_accesses::total 70691 # number of demand (read+write) accesses
|
|
system.cpu4.l1c.overall_accesses::cpu4 70691 # number of overall (read+write) accesses
|
|
system.cpu4.l1c.overall_accesses::total 70691 # number of overall (read+write) accesses
|
|
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.803980 # miss rate for ReadReq accesses
|
|
system.cpu4.l1c.ReadReq_miss_rate::total 0.803980 # miss rate for ReadReq accesses
|
|
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953941 # miss rate for WriteReq accesses
|
|
system.cpu4.l1c.WriteReq_miss_rate::total 0.953941 # miss rate for WriteReq accesses
|
|
system.cpu4.l1c.demand_miss_rate::cpu4 0.857775 # miss rate for demand accesses
|
|
system.cpu4.l1c.demand_miss_rate::total 0.857775 # miss rate for demand accesses
|
|
system.cpu4.l1c.overall_miss_rate::cpu4 0.857775 # miss rate for overall accesses
|
|
system.cpu4.l1c.overall_miss_rate::total 0.857775 # miss rate for overall accesses
|
|
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18456.687730 # average ReadReq miss latency
|
|
system.cpu4.l1c.ReadReq_avg_miss_latency::total 18456.687730 # average ReadReq miss latency
|
|
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23158.775040 # average WriteReq miss latency
|
|
system.cpu4.l1c.WriteReq_avg_miss_latency::total 23158.775040 # average WriteReq miss latency
|
|
system.cpu4.l1c.demand_avg_miss_latency::cpu4 20332.575292 # average overall miss latency
|
|
system.cpu4.l1c.demand_avg_miss_latency::total 20332.575292 # average overall miss latency
|
|
system.cpu4.l1c.overall_avg_miss_latency::cpu4 20332.575292 # average overall miss latency
|
|
system.cpu4.l1c.overall_avg_miss_latency::total 20332.575292 # average overall miss latency
|
|
system.cpu4.l1c.blocked_cycles::no_mshrs 801696 # number of cycles access was blocked
|
|
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu4.l1c.blocked::no_mshrs 65950 # number of cycles access was blocked
|
|
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.156118 # average number of cycles each access was blocked
|
|
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu4.l1c.writebacks::writebacks 9921 # number of writebacks
|
|
system.cpu4.l1c.writebacks::total 9921 # number of writebacks
|
|
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36446 # number of ReadReq MSHR misses
|
|
system.cpu4.l1c.ReadReq_mshr_misses::total 36446 # number of ReadReq MSHR misses
|
|
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24191 # number of WriteReq MSHR misses
|
|
system.cpu4.l1c.WriteReq_mshr_misses::total 24191 # number of WriteReq MSHR misses
|
|
system.cpu4.l1c.demand_mshr_misses::cpu4 60637 # number of demand (read+write) MSHR misses
|
|
system.cpu4.l1c.demand_mshr_misses::total 60637 # number of demand (read+write) MSHR misses
|
|
system.cpu4.l1c.overall_mshr_misses::cpu4 60637 # number of overall MSHR misses
|
|
system.cpu4.l1c.overall_mshr_misses::total 60637 # number of overall MSHR misses
|
|
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9877 # number of ReadReq MSHR uncacheable
|
|
system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9877 # number of ReadReq MSHR uncacheable
|
|
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5522 # number of WriteReq MSHR uncacheable
|
|
system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable
|
|
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15399 # number of overall MSHR uncacheable misses
|
|
system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15399 # number of overall MSHR uncacheable misses
|
|
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 636227441 # number of ReadReq MSHR miss cycles
|
|
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 636227441 # number of ReadReq MSHR miss cycles
|
|
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 536043927 # number of WriteReq MSHR miss cycles
|
|
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 536043927 # number of WriteReq MSHR miss cycles
|
|
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1172271368 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu4.l1c.demand_mshr_miss_latency::total 1172271368 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1172271368 # number of overall MSHR miss cycles
|
|
system.cpu4.l1c.overall_mshr_miss_latency::total 1172271368 # number of overall MSHR miss cycles
|
|
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 739458183 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 739458183 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 739458183 # number of overall MSHR uncacheable cycles
|
|
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 739458183 # number of overall MSHR uncacheable cycles
|
|
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.803980 # mshr miss rate for ReadReq accesses
|
|
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.803980 # mshr miss rate for ReadReq accesses
|
|
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953941 # mshr miss rate for WriteReq accesses
|
|
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953941 # mshr miss rate for WriteReq accesses
|
|
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857775 # mshr miss rate for demand accesses
|
|
system.cpu4.l1c.demand_mshr_miss_rate::total 0.857775 # mshr miss rate for demand accesses
|
|
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857775 # mshr miss rate for overall accesses
|
|
system.cpu4.l1c.overall_mshr_miss_rate::total 0.857775 # mshr miss rate for overall accesses
|
|
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17456.715168 # average ReadReq mshr miss latency
|
|
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17456.715168 # average ReadReq mshr miss latency
|
|
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22158.816378 # average WriteReq mshr miss latency
|
|
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22158.816378 # average WriteReq mshr miss latency
|
|
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19332.608275 # average overall mshr miss latency
|
|
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19332.608275 # average overall mshr miss latency
|
|
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19332.608275 # average overall mshr miss latency
|
|
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19332.608275 # average overall mshr miss latency
|
|
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74866.678445 # average ReadReq mshr uncacheable latency
|
|
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74866.678445 # average ReadReq mshr uncacheable latency
|
|
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48019.883304 # average overall mshr uncacheable latency
|
|
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48019.883304 # average overall mshr uncacheable latency
|
|
system.cpu5.num_reads 99665 # number of read accesses completed
|
|
system.cpu5.num_writes 55439 # number of write accesses completed
|
|
system.cpu5.l1c.tags.replacements 22286 # number of replacements
|
|
system.cpu5.l1c.tags.tagsinuse 391.859990 # Cycle average of tags in use
|
|
system.cpu5.l1c.tags.total_refs 13458 # Total number of references to valid blocks.
|
|
system.cpu5.l1c.tags.sampled_refs 22703 # Sample count of references to valid blocks.
|
|
system.cpu5.l1c.tags.avg_refs 0.592785 # Average number of references to valid blocks.
|
|
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu5.l1c.tags.occ_blocks::cpu5 391.859990 # Average occupied blocks per requestor
|
|
system.cpu5.l1c.tags.occ_percent::cpu5 0.765352 # Average percentage of cache occupancy
|
|
system.cpu5.l1c.tags.occ_percent::total 0.765352 # Average percentage of cache occupancy
|
|
system.cpu5.l1c.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id
|
|
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id
|
|
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
|
|
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id
|
|
system.cpu5.l1c.tags.tag_accesses 338594 # Number of tag accesses
|
|
system.cpu5.l1c.tags.data_accesses 338594 # Number of data accesses
|
|
system.cpu5.l1c.ReadReq_hits::cpu5 8649 # number of ReadReq hits
|
|
system.cpu5.l1c.ReadReq_hits::total 8649 # number of ReadReq hits
|
|
system.cpu5.l1c.WriteReq_hits::cpu5 1196 # number of WriteReq hits
|
|
system.cpu5.l1c.WriteReq_hits::total 1196 # number of WriteReq hits
|
|
system.cpu5.l1c.demand_hits::cpu5 9845 # number of demand (read+write) hits
|
|
system.cpu5.l1c.demand_hits::total 9845 # number of demand (read+write) hits
|
|
system.cpu5.l1c.overall_hits::cpu5 9845 # number of overall hits
|
|
system.cpu5.l1c.overall_hits::total 9845 # number of overall hits
|
|
system.cpu5.l1c.ReadReq_misses::cpu5 36574 # number of ReadReq misses
|
|
system.cpu5.l1c.ReadReq_misses::total 36574 # number of ReadReq misses
|
|
system.cpu5.l1c.WriteReq_misses::cpu5 24003 # number of WriteReq misses
|
|
system.cpu5.l1c.WriteReq_misses::total 24003 # number of WriteReq misses
|
|
system.cpu5.l1c.demand_misses::cpu5 60577 # number of demand (read+write) misses
|
|
system.cpu5.l1c.demand_misses::total 60577 # number of demand (read+write) misses
|
|
system.cpu5.l1c.overall_misses::cpu5 60577 # number of overall misses
|
|
system.cpu5.l1c.overall_misses::total 60577 # number of overall misses
|
|
system.cpu5.l1c.ReadReq_miss_latency::cpu5 671451246 # number of ReadReq miss cycles
|
|
system.cpu5.l1c.ReadReq_miss_latency::total 671451246 # number of ReadReq miss cycles
|
|
system.cpu5.l1c.WriteReq_miss_latency::cpu5 559158053 # number of WriteReq miss cycles
|
|
system.cpu5.l1c.WriteReq_miss_latency::total 559158053 # number of WriteReq miss cycles
|
|
system.cpu5.l1c.demand_miss_latency::cpu5 1230609299 # number of demand (read+write) miss cycles
|
|
system.cpu5.l1c.demand_miss_latency::total 1230609299 # number of demand (read+write) miss cycles
|
|
system.cpu5.l1c.overall_miss_latency::cpu5 1230609299 # number of overall miss cycles
|
|
system.cpu5.l1c.overall_miss_latency::total 1230609299 # number of overall miss cycles
|
|
system.cpu5.l1c.ReadReq_accesses::cpu5 45223 # number of ReadReq accesses(hits+misses)
|
|
system.cpu5.l1c.ReadReq_accesses::total 45223 # number of ReadReq accesses(hits+misses)
|
|
system.cpu5.l1c.WriteReq_accesses::cpu5 25199 # number of WriteReq accesses(hits+misses)
|
|
system.cpu5.l1c.WriteReq_accesses::total 25199 # number of WriteReq accesses(hits+misses)
|
|
system.cpu5.l1c.demand_accesses::cpu5 70422 # number of demand (read+write) accesses
|
|
system.cpu5.l1c.demand_accesses::total 70422 # number of demand (read+write) accesses
|
|
system.cpu5.l1c.overall_accesses::cpu5 70422 # number of overall (read+write) accesses
|
|
system.cpu5.l1c.overall_accesses::total 70422 # number of overall (read+write) accesses
|
|
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808748 # miss rate for ReadReq accesses
|
|
system.cpu5.l1c.ReadReq_miss_rate::total 0.808748 # miss rate for ReadReq accesses
|
|
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952538 # miss rate for WriteReq accesses
|
|
system.cpu5.l1c.WriteReq_miss_rate::total 0.952538 # miss rate for WriteReq accesses
|
|
system.cpu5.l1c.demand_miss_rate::cpu5 0.860200 # miss rate for demand accesses
|
|
system.cpu5.l1c.demand_miss_rate::total 0.860200 # miss rate for demand accesses
|
|
system.cpu5.l1c.overall_miss_rate::cpu5 0.860200 # miss rate for overall accesses
|
|
system.cpu5.l1c.overall_miss_rate::total 0.860200 # miss rate for overall accesses
|
|
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18358.704161 # average ReadReq miss latency
|
|
system.cpu5.l1c.ReadReq_avg_miss_latency::total 18358.704161 # average ReadReq miss latency
|
|
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23295.340291 # average WriteReq miss latency
|
|
system.cpu5.l1c.WriteReq_avg_miss_latency::total 23295.340291 # average WriteReq miss latency
|
|
system.cpu5.l1c.demand_avg_miss_latency::cpu5 20314.794377 # average overall miss latency
|
|
system.cpu5.l1c.demand_avg_miss_latency::total 20314.794377 # average overall miss latency
|
|
system.cpu5.l1c.overall_avg_miss_latency::cpu5 20314.794377 # average overall miss latency
|
|
system.cpu5.l1c.overall_avg_miss_latency::total 20314.794377 # average overall miss latency
|
|
system.cpu5.l1c.blocked_cycles::no_mshrs 802483 # number of cycles access was blocked
|
|
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu5.l1c.blocked::no_mshrs 66128 # number of cycles access was blocked
|
|
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.135298 # average number of cycles each access was blocked
|
|
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu5.l1c.writebacks::writebacks 9886 # number of writebacks
|
|
system.cpu5.l1c.writebacks::total 9886 # number of writebacks
|
|
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36574 # number of ReadReq MSHR misses
|
|
system.cpu5.l1c.ReadReq_mshr_misses::total 36574 # number of ReadReq MSHR misses
|
|
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24003 # number of WriteReq MSHR misses
|
|
system.cpu5.l1c.WriteReq_mshr_misses::total 24003 # number of WriteReq MSHR misses
|
|
system.cpu5.l1c.demand_mshr_misses::cpu5 60577 # number of demand (read+write) MSHR misses
|
|
system.cpu5.l1c.demand_mshr_misses::total 60577 # number of demand (read+write) MSHR misses
|
|
system.cpu5.l1c.overall_mshr_misses::cpu5 60577 # number of overall MSHR misses
|
|
system.cpu5.l1c.overall_mshr_misses::total 60577 # number of overall MSHR misses
|
|
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9910 # number of ReadReq MSHR uncacheable
|
|
system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9910 # number of ReadReq MSHR uncacheable
|
|
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5451 # number of WriteReq MSHR uncacheable
|
|
system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5451 # number of WriteReq MSHR uncacheable
|
|
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15361 # number of overall MSHR uncacheable misses
|
|
system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15361 # number of overall MSHR uncacheable misses
|
|
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 634877246 # number of ReadReq MSHR miss cycles
|
|
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 634877246 # number of ReadReq MSHR miss cycles
|
|
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 535156053 # number of WriteReq MSHR miss cycles
|
|
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 535156053 # number of WriteReq MSHR miss cycles
|
|
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1170033299 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu5.l1c.demand_mshr_miss_latency::total 1170033299 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1170033299 # number of overall MSHR miss cycles
|
|
system.cpu5.l1c.overall_mshr_miss_latency::total 1170033299 # number of overall MSHR miss cycles
|
|
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 742019082 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 742019082 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 742019082 # number of overall MSHR uncacheable cycles
|
|
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 742019082 # number of overall MSHR uncacheable cycles
|
|
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808748 # mshr miss rate for ReadReq accesses
|
|
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808748 # mshr miss rate for ReadReq accesses
|
|
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952538 # mshr miss rate for WriteReq accesses
|
|
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952538 # mshr miss rate for WriteReq accesses
|
|
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860200 # mshr miss rate for demand accesses
|
|
system.cpu5.l1c.demand_mshr_miss_rate::total 0.860200 # mshr miss rate for demand accesses
|
|
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860200 # mshr miss rate for overall accesses
|
|
system.cpu5.l1c.overall_mshr_miss_rate::total 0.860200 # mshr miss rate for overall accesses
|
|
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17358.704161 # average ReadReq mshr miss latency
|
|
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17358.704161 # average ReadReq mshr miss latency
|
|
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22295.381952 # average WriteReq mshr miss latency
|
|
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22295.381952 # average WriteReq mshr miss latency
|
|
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19314.810885 # average overall mshr miss latency
|
|
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19314.810885 # average overall mshr miss latency
|
|
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19314.810885 # average overall mshr miss latency
|
|
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19314.810885 # average overall mshr miss latency
|
|
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74875.790313 # average ReadReq mshr uncacheable latency
|
|
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74875.790313 # average ReadReq mshr uncacheable latency
|
|
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 48305.389102 # average overall mshr uncacheable latency
|
|
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 48305.389102 # average overall mshr uncacheable latency
|
|
system.cpu6.num_reads 99712 # number of read accesses completed
|
|
system.cpu6.num_writes 55282 # number of write accesses completed
|
|
system.cpu6.l1c.tags.replacements 22239 # number of replacements
|
|
system.cpu6.l1c.tags.tagsinuse 392.046110 # Cycle average of tags in use
|
|
system.cpu6.l1c.tags.total_refs 13503 # Total number of references to valid blocks.
|
|
system.cpu6.l1c.tags.sampled_refs 22637 # Sample count of references to valid blocks.
|
|
system.cpu6.l1c.tags.avg_refs 0.596501 # Average number of references to valid blocks.
|
|
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu6.l1c.tags.occ_blocks::cpu6 392.046110 # Average occupied blocks per requestor
|
|
system.cpu6.l1c.tags.occ_percent::cpu6 0.765715 # Average percentage of cache occupancy
|
|
system.cpu6.l1c.tags.occ_percent::total 0.765715 # Average percentage of cache occupancy
|
|
system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
|
|
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id
|
|
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
|
|
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
|
|
system.cpu6.l1c.tags.tag_accesses 338073 # Number of tag accesses
|
|
system.cpu6.l1c.tags.data_accesses 338073 # Number of data accesses
|
|
system.cpu6.l1c.ReadReq_hits::cpu6 8758 # number of ReadReq hits
|
|
system.cpu6.l1c.ReadReq_hits::total 8758 # number of ReadReq hits
|
|
system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits
|
|
system.cpu6.l1c.WriteReq_hits::total 1067 # number of WriteReq hits
|
|
system.cpu6.l1c.demand_hits::cpu6 9825 # number of demand (read+write) hits
|
|
system.cpu6.l1c.demand_hits::total 9825 # number of demand (read+write) hits
|
|
system.cpu6.l1c.overall_hits::cpu6 9825 # number of overall hits
|
|
system.cpu6.l1c.overall_hits::total 9825 # number of overall hits
|
|
system.cpu6.l1c.ReadReq_misses::cpu6 36548 # number of ReadReq misses
|
|
system.cpu6.l1c.ReadReq_misses::total 36548 # number of ReadReq misses
|
|
system.cpu6.l1c.WriteReq_misses::cpu6 23952 # number of WriteReq misses
|
|
system.cpu6.l1c.WriteReq_misses::total 23952 # number of WriteReq misses
|
|
system.cpu6.l1c.demand_misses::cpu6 60500 # number of demand (read+write) misses
|
|
system.cpu6.l1c.demand_misses::total 60500 # number of demand (read+write) misses
|
|
system.cpu6.l1c.overall_misses::cpu6 60500 # number of overall misses
|
|
system.cpu6.l1c.overall_misses::total 60500 # number of overall misses
|
|
system.cpu6.l1c.ReadReq_miss_latency::cpu6 674135322 # number of ReadReq miss cycles
|
|
system.cpu6.l1c.ReadReq_miss_latency::total 674135322 # number of ReadReq miss cycles
|
|
system.cpu6.l1c.WriteReq_miss_latency::cpu6 560982121 # number of WriteReq miss cycles
|
|
system.cpu6.l1c.WriteReq_miss_latency::total 560982121 # number of WriteReq miss cycles
|
|
system.cpu6.l1c.demand_miss_latency::cpu6 1235117443 # number of demand (read+write) miss cycles
|
|
system.cpu6.l1c.demand_miss_latency::total 1235117443 # number of demand (read+write) miss cycles
|
|
system.cpu6.l1c.overall_miss_latency::cpu6 1235117443 # number of overall miss cycles
|
|
system.cpu6.l1c.overall_miss_latency::total 1235117443 # number of overall miss cycles
|
|
system.cpu6.l1c.ReadReq_accesses::cpu6 45306 # number of ReadReq accesses(hits+misses)
|
|
system.cpu6.l1c.ReadReq_accesses::total 45306 # number of ReadReq accesses(hits+misses)
|
|
system.cpu6.l1c.WriteReq_accesses::cpu6 25019 # number of WriteReq accesses(hits+misses)
|
|
system.cpu6.l1c.WriteReq_accesses::total 25019 # number of WriteReq accesses(hits+misses)
|
|
system.cpu6.l1c.demand_accesses::cpu6 70325 # number of demand (read+write) accesses
|
|
system.cpu6.l1c.demand_accesses::total 70325 # number of demand (read+write) accesses
|
|
system.cpu6.l1c.overall_accesses::cpu6 70325 # number of overall (read+write) accesses
|
|
system.cpu6.l1c.overall_accesses::total 70325 # number of overall (read+write) accesses
|
|
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806692 # miss rate for ReadReq accesses
|
|
system.cpu6.l1c.ReadReq_miss_rate::total 0.806692 # miss rate for ReadReq accesses
|
|
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.957352 # miss rate for WriteReq accesses
|
|
system.cpu6.l1c.WriteReq_miss_rate::total 0.957352 # miss rate for WriteReq accesses
|
|
system.cpu6.l1c.demand_miss_rate::cpu6 0.860292 # miss rate for demand accesses
|
|
system.cpu6.l1c.demand_miss_rate::total 0.860292 # miss rate for demand accesses
|
|
system.cpu6.l1c.overall_miss_rate::cpu6 0.860292 # miss rate for overall accesses
|
|
system.cpu6.l1c.overall_miss_rate::total 0.860292 # miss rate for overall accesses
|
|
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18445.204170 # average ReadReq miss latency
|
|
system.cpu6.l1c.ReadReq_avg_miss_latency::total 18445.204170 # average ReadReq miss latency
|
|
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23421.097236 # average WriteReq miss latency
|
|
system.cpu6.l1c.WriteReq_avg_miss_latency::total 23421.097236 # average WriteReq miss latency
|
|
system.cpu6.l1c.demand_avg_miss_latency::cpu6 20415.164347 # average overall miss latency
|
|
system.cpu6.l1c.demand_avg_miss_latency::total 20415.164347 # average overall miss latency
|
|
system.cpu6.l1c.overall_avg_miss_latency::cpu6 20415.164347 # average overall miss latency
|
|
system.cpu6.l1c.overall_avg_miss_latency::total 20415.164347 # average overall miss latency
|
|
system.cpu6.l1c.blocked_cycles::no_mshrs 802988 # number of cycles access was blocked
|
|
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu6.l1c.blocked::no_mshrs 65839 # number of cycles access was blocked
|
|
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.196236 # average number of cycles each access was blocked
|
|
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu6.l1c.writebacks::writebacks 9826 # number of writebacks
|
|
system.cpu6.l1c.writebacks::total 9826 # number of writebacks
|
|
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36548 # number of ReadReq MSHR misses
|
|
system.cpu6.l1c.ReadReq_mshr_misses::total 36548 # number of ReadReq MSHR misses
|
|
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23952 # number of WriteReq MSHR misses
|
|
system.cpu6.l1c.WriteReq_mshr_misses::total 23952 # number of WriteReq MSHR misses
|
|
system.cpu6.l1c.demand_mshr_misses::cpu6 60500 # number of demand (read+write) MSHR misses
|
|
system.cpu6.l1c.demand_mshr_misses::total 60500 # number of demand (read+write) MSHR misses
|
|
system.cpu6.l1c.overall_mshr_misses::cpu6 60500 # number of overall MSHR misses
|
|
system.cpu6.l1c.overall_mshr_misses::total 60500 # number of overall MSHR misses
|
|
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9861 # number of ReadReq MSHR uncacheable
|
|
system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9861 # number of ReadReq MSHR uncacheable
|
|
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5592 # number of WriteReq MSHR uncacheable
|
|
system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5592 # number of WriteReq MSHR uncacheable
|
|
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15453 # number of overall MSHR uncacheable misses
|
|
system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15453 # number of overall MSHR uncacheable misses
|
|
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 637587322 # number of ReadReq MSHR miss cycles
|
|
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 637587322 # number of ReadReq MSHR miss cycles
|
|
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 537030121 # number of WriteReq MSHR miss cycles
|
|
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 537030121 # number of WriteReq MSHR miss cycles
|
|
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1174617443 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu6.l1c.demand_mshr_miss_latency::total 1174617443 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1174617443 # number of overall MSHR miss cycles
|
|
system.cpu6.l1c.overall_mshr_miss_latency::total 1174617443 # number of overall MSHR miss cycles
|
|
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 737828201 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 737828201 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 737828201 # number of overall MSHR uncacheable cycles
|
|
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 737828201 # number of overall MSHR uncacheable cycles
|
|
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806692 # mshr miss rate for ReadReq accesses
|
|
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806692 # mshr miss rate for ReadReq accesses
|
|
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.957352 # mshr miss rate for WriteReq accesses
|
|
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.957352 # mshr miss rate for WriteReq accesses
|
|
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860292 # mshr miss rate for demand accesses
|
|
system.cpu6.l1c.demand_mshr_miss_rate::total 0.860292 # mshr miss rate for demand accesses
|
|
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860292 # mshr miss rate for overall accesses
|
|
system.cpu6.l1c.overall_mshr_miss_rate::total 0.860292 # mshr miss rate for overall accesses
|
|
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17445.204170 # average ReadReq mshr miss latency
|
|
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17445.204170 # average ReadReq mshr miss latency
|
|
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22421.097236 # average WriteReq mshr miss latency
|
|
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22421.097236 # average WriteReq mshr miss latency
|
|
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19415.164347 # average overall mshr miss latency
|
|
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19415.164347 # average overall mshr miss latency
|
|
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19415.164347 # average overall mshr miss latency
|
|
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19415.164347 # average overall mshr miss latency
|
|
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74822.857824 # average ReadReq mshr uncacheable latency
|
|
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74822.857824 # average ReadReq mshr uncacheable latency
|
|
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 47746.599431 # average overall mshr uncacheable latency
|
|
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 47746.599431 # average overall mshr uncacheable latency
|
|
system.cpu7.num_reads 99031 # number of read accesses completed
|
|
system.cpu7.num_writes 54931 # number of write accesses completed
|
|
system.cpu7.l1c.tags.replacements 22638 # number of replacements
|
|
system.cpu7.l1c.tags.tagsinuse 391.993848 # Cycle average of tags in use
|
|
system.cpu7.l1c.tags.total_refs 13556 # Total number of references to valid blocks.
|
|
system.cpu7.l1c.tags.sampled_refs 23038 # Sample count of references to valid blocks.
|
|
system.cpu7.l1c.tags.avg_refs 0.588419 # Average number of references to valid blocks.
|
|
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu7.l1c.tags.occ_blocks::cpu7 391.993848 # Average occupied blocks per requestor
|
|
system.cpu7.l1c.tags.occ_percent::cpu7 0.765613 # Average percentage of cache occupancy
|
|
system.cpu7.l1c.tags.occ_percent::total 0.765613 # Average percentage of cache occupancy
|
|
system.cpu7.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
|
|
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id
|
|
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
|
|
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
|
|
system.cpu7.l1c.tags.tag_accesses 339734 # Number of tag accesses
|
|
system.cpu7.l1c.tags.data_accesses 339734 # Number of data accesses
|
|
system.cpu7.l1c.ReadReq_hits::cpu7 8818 # number of ReadReq hits
|
|
system.cpu7.l1c.ReadReq_hits::total 8818 # number of ReadReq hits
|
|
system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits
|
|
system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits
|
|
system.cpu7.l1c.demand_hits::cpu7 9966 # number of demand (read+write) hits
|
|
system.cpu7.l1c.demand_hits::total 9966 # number of demand (read+write) hits
|
|
system.cpu7.l1c.overall_hits::cpu7 9966 # number of overall hits
|
|
system.cpu7.l1c.overall_hits::total 9966 # number of overall hits
|
|
system.cpu7.l1c.ReadReq_misses::cpu7 36554 # number of ReadReq misses
|
|
system.cpu7.l1c.ReadReq_misses::total 36554 # number of ReadReq misses
|
|
system.cpu7.l1c.WriteReq_misses::cpu7 24149 # number of WriteReq misses
|
|
system.cpu7.l1c.WriteReq_misses::total 24149 # number of WriteReq misses
|
|
system.cpu7.l1c.demand_misses::cpu7 60703 # number of demand (read+write) misses
|
|
system.cpu7.l1c.demand_misses::total 60703 # number of demand (read+write) misses
|
|
system.cpu7.l1c.overall_misses::cpu7 60703 # number of overall misses
|
|
system.cpu7.l1c.overall_misses::total 60703 # number of overall misses
|
|
system.cpu7.l1c.ReadReq_miss_latency::cpu7 675691654 # number of ReadReq miss cycles
|
|
system.cpu7.l1c.ReadReq_miss_latency::total 675691654 # number of ReadReq miss cycles
|
|
system.cpu7.l1c.WriteReq_miss_latency::cpu7 565139421 # number of WriteReq miss cycles
|
|
system.cpu7.l1c.WriteReq_miss_latency::total 565139421 # number of WriteReq miss cycles
|
|
system.cpu7.l1c.demand_miss_latency::cpu7 1240831075 # number of demand (read+write) miss cycles
|
|
system.cpu7.l1c.demand_miss_latency::total 1240831075 # number of demand (read+write) miss cycles
|
|
system.cpu7.l1c.overall_miss_latency::cpu7 1240831075 # number of overall miss cycles
|
|
system.cpu7.l1c.overall_miss_latency::total 1240831075 # number of overall miss cycles
|
|
system.cpu7.l1c.ReadReq_accesses::cpu7 45372 # number of ReadReq accesses(hits+misses)
|
|
system.cpu7.l1c.ReadReq_accesses::total 45372 # number of ReadReq accesses(hits+misses)
|
|
system.cpu7.l1c.WriteReq_accesses::cpu7 25297 # number of WriteReq accesses(hits+misses)
|
|
system.cpu7.l1c.WriteReq_accesses::total 25297 # number of WriteReq accesses(hits+misses)
|
|
system.cpu7.l1c.demand_accesses::cpu7 70669 # number of demand (read+write) accesses
|
|
system.cpu7.l1c.demand_accesses::total 70669 # number of demand (read+write) accesses
|
|
system.cpu7.l1c.overall_accesses::cpu7 70669 # number of overall (read+write) accesses
|
|
system.cpu7.l1c.overall_accesses::total 70669 # number of overall (read+write) accesses
|
|
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805651 # miss rate for ReadReq accesses
|
|
system.cpu7.l1c.ReadReq_miss_rate::total 0.805651 # miss rate for ReadReq accesses
|
|
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954619 # miss rate for WriteReq accesses
|
|
system.cpu7.l1c.WriteReq_miss_rate::total 0.954619 # miss rate for WriteReq accesses
|
|
system.cpu7.l1c.demand_miss_rate::cpu7 0.858976 # miss rate for demand accesses
|
|
system.cpu7.l1c.demand_miss_rate::total 0.858976 # miss rate for demand accesses
|
|
system.cpu7.l1c.overall_miss_rate::cpu7 0.858976 # miss rate for overall accesses
|
|
system.cpu7.l1c.overall_miss_rate::total 0.858976 # miss rate for overall accesses
|
|
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18484.752804 # average ReadReq miss latency
|
|
system.cpu7.l1c.ReadReq_avg_miss_latency::total 18484.752804 # average ReadReq miss latency
|
|
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23402.187296 # average WriteReq miss latency
|
|
system.cpu7.l1c.WriteReq_avg_miss_latency::total 23402.187296 # average WriteReq miss latency
|
|
system.cpu7.l1c.demand_avg_miss_latency::cpu7 20441.017330 # average overall miss latency
|
|
system.cpu7.l1c.demand_avg_miss_latency::total 20441.017330 # average overall miss latency
|
|
system.cpu7.l1c.overall_avg_miss_latency::cpu7 20441.017330 # average overall miss latency
|
|
system.cpu7.l1c.overall_avg_miss_latency::total 20441.017330 # average overall miss latency
|
|
system.cpu7.l1c.blocked_cycles::no_mshrs 799894 # number of cycles access was blocked
|
|
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu7.l1c.blocked::no_mshrs 65859 # number of cycles access was blocked
|
|
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.145553 # average number of cycles each access was blocked
|
|
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu7.l1c.writebacks::writebacks 9912 # number of writebacks
|
|
system.cpu7.l1c.writebacks::total 9912 # number of writebacks
|
|
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36554 # number of ReadReq MSHR misses
|
|
system.cpu7.l1c.ReadReq_mshr_misses::total 36554 # number of ReadReq MSHR misses
|
|
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24149 # number of WriteReq MSHR misses
|
|
system.cpu7.l1c.WriteReq_mshr_misses::total 24149 # number of WriteReq MSHR misses
|
|
system.cpu7.l1c.demand_mshr_misses::cpu7 60703 # number of demand (read+write) MSHR misses
|
|
system.cpu7.l1c.demand_mshr_misses::total 60703 # number of demand (read+write) MSHR misses
|
|
system.cpu7.l1c.overall_mshr_misses::cpu7 60703 # number of overall MSHR misses
|
|
system.cpu7.l1c.overall_mshr_misses::total 60703 # number of overall MSHR misses
|
|
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9740 # number of ReadReq MSHR uncacheable
|
|
system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9740 # number of ReadReq MSHR uncacheable
|
|
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5359 # number of WriteReq MSHR uncacheable
|
|
system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5359 # number of WriteReq MSHR uncacheable
|
|
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15099 # number of overall MSHR uncacheable misses
|
|
system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15099 # number of overall MSHR uncacheable misses
|
|
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 639138654 # number of ReadReq MSHR miss cycles
|
|
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 639138654 # number of ReadReq MSHR miss cycles
|
|
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 540990421 # number of WriteReq MSHR miss cycles
|
|
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 540990421 # number of WriteReq MSHR miss cycles
|
|
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1180129075 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu7.l1c.demand_mshr_miss_latency::total 1180129075 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1180129075 # number of overall MSHR miss cycles
|
|
system.cpu7.l1c.overall_mshr_miss_latency::total 1180129075 # number of overall MSHR miss cycles
|
|
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 730529776 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 730529776 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 730529776 # number of overall MSHR uncacheable cycles
|
|
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 730529776 # number of overall MSHR uncacheable cycles
|
|
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805651 # mshr miss rate for ReadReq accesses
|
|
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805651 # mshr miss rate for ReadReq accesses
|
|
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954619 # mshr miss rate for WriteReq accesses
|
|
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954619 # mshr miss rate for WriteReq accesses
|
|
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858976 # mshr miss rate for demand accesses
|
|
system.cpu7.l1c.demand_mshr_miss_rate::total 0.858976 # mshr miss rate for demand accesses
|
|
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858976 # mshr miss rate for overall accesses
|
|
system.cpu7.l1c.overall_mshr_miss_rate::total 0.858976 # mshr miss rate for overall accesses
|
|
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17484.780161 # average ReadReq mshr miss latency
|
|
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17484.780161 # average ReadReq mshr miss latency
|
|
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22402.187296 # average WriteReq mshr miss latency
|
|
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22402.187296 # average WriteReq mshr miss latency
|
|
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19441.033804 # average overall mshr miss latency
|
|
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19441.033804 # average overall mshr miss latency
|
|
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19441.033804 # average overall mshr miss latency
|
|
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19441.033804 # average overall mshr miss latency
|
|
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75003.057084 # average ReadReq mshr uncacheable latency
|
|
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.057084 # average ReadReq mshr uncacheable latency
|
|
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 48382.659514 # average overall mshr uncacheable latency
|
|
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 48382.659514 # average overall mshr uncacheable latency
|
|
system.l2c.tags.replacements 13688 # number of replacements
|
|
system.l2c.tags.tagsinuse 782.559938 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 164623 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 14478 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 11.370562 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 726.348525 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0 6.677170 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1 6.765222 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2 6.924842 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3 7.010620 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu4 7.585654 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu5 6.814501 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu6 7.441816 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu7 6.991588 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.709325 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0 0.006521 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1 0.006607 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2 0.006763 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3 0.006846 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu4 0.007408 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu5 0.006655 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu6 0.007267 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu7 0.006828 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.764219 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 664 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 2107372 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 2107372 # Number of data accesses
|
|
system.l2c.WritebackDirty_hits::writebacks 77671 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 77671 # number of WritebackDirty hits
|
|
system.l2c.UpgradeReq_hits::cpu0 272 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1 284 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2 276 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu3 280 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu4 255 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu5 283 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu6 239 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu7 262 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 2151 # number of UpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0 1876 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1 1780 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2 1805 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu3 1782 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu4 1816 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu5 1727 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu6 1803 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu7 1809 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 14398 # number of ReadExReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0 10873 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1 10958 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu2 10812 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu3 11007 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu4 10755 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu5 10989 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu6 11012 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu7 10808 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 87214 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0 12749 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1 12738 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2 12617 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3 12789 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu4 12571 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu5 12716 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu6 12815 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu7 12617 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 101612 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0 12749 # number of overall hits
|
|
system.l2c.overall_hits::cpu1 12738 # number of overall hits
|
|
system.l2c.overall_hits::cpu2 12617 # number of overall hits
|
|
system.l2c.overall_hits::cpu3 12789 # number of overall hits
|
|
system.l2c.overall_hits::cpu4 12571 # number of overall hits
|
|
system.l2c.overall_hits::cpu5 12716 # number of overall hits
|
|
system.l2c.overall_hits::cpu6 12815 # number of overall hits
|
|
system.l2c.overall_hits::cpu7 12617 # number of overall hits
|
|
system.l2c.overall_hits::total 101612 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0 2119 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1 2003 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2 2061 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3 2101 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu4 1934 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu5 2026 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu6 2139 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu7 2027 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 16410 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0 4596 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1 4672 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2 4641 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3 4561 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu4 4696 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu5 4677 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu6 4637 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu7 4651 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 37131 # number of ReadExReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0 698 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1 712 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu2 734 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu3 737 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu4 740 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu5 681 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu6 738 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu7 697 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 5737 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0 5294 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2 5375 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3 5298 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu4 5436 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu5 5358 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu6 5375 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu7 5348 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 42868 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0 5294 # number of overall misses
|
|
system.l2c.overall_misses::cpu1 5384 # number of overall misses
|
|
system.l2c.overall_misses::cpu2 5375 # number of overall misses
|
|
system.l2c.overall_misses::cpu3 5298 # number of overall misses
|
|
system.l2c.overall_misses::cpu4 5436 # number of overall misses
|
|
system.l2c.overall_misses::cpu5 5358 # number of overall misses
|
|
system.l2c.overall_misses::cpu6 5375 # number of overall misses
|
|
system.l2c.overall_misses::cpu7 5348 # number of overall misses
|
|
system.l2c.overall_misses::total 42868 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu0 34306000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1 32515999 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu2 33970000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu3 33665000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu4 30524499 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu5 33417998 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu6 35180998 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu7 31945000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 265525494 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0 148628443 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1 153234943 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2 151708946 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3 148204781 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu4 153854439 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu5 151693945 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu6 152734439 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu7 151392920 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 1211452856 # number of ReadExReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0 49327224 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1 49579908 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu2 50488876 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu3 50929398 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu4 51564743 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu5 47695729 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu6 51087902 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu7 48881401 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 399555181 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0 197955667 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1 202814851 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2 202197822 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3 199134179 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu4 205419182 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu5 199389674 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu6 203822341 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu7 200274321 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 1611008037 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0 197955667 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1 202814851 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2 202197822 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3 199134179 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu4 205419182 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu5 199389674 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu6 203822341 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu7 200274321 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 1611008037 # number of overall miss cycles
|
|
system.l2c.WritebackDirty_accesses::writebacks 77671 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 77671 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0 2391 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1 2287 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2 2337 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3 2381 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu4 2189 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu5 2309 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu6 2378 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu7 2289 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 18561 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0 6472 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1 6452 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2 6446 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3 6343 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu4 6512 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu5 6404 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu6 6440 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu7 6460 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 51529 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0 11571 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1 11670 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu2 11546 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu3 11744 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu4 11495 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu5 11670 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu6 11750 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu7 11505 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 92951 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0 18043 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1 18122 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2 17992 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3 18087 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu4 18007 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu5 18074 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu6 18190 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu7 17965 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 144480 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0 18043 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1 18122 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2 17992 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3 18087 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu4 18007 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu5 18074 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu6 18190 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu7 17965 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 144480 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0 0.886240 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1 0.875820 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2 0.881900 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3 0.882402 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu4 0.883508 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu5 0.877436 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu6 0.899495 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu7 0.885540 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.884112 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0 0.710136 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1 0.724117 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2 0.719981 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3 0.719060 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu4 0.721130 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu5 0.730325 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu6 0.720031 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu7 0.719969 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.720585 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0 0.060323 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1 0.061011 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu2 0.063572 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu3 0.062755 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu4 0.064376 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu5 0.058355 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu6 0.062809 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu7 0.060582 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.061721 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0 0.293410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1 0.297097 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2 0.298744 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3 0.292918 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu4 0.301883 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu5 0.296448 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu6 0.295492 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu7 0.297690 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.296705 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0 0.293410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1 0.297097 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2 0.298744 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3 0.292918 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu4 0.301883 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu5 0.296448 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu6 0.295492 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu7 0.297690 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.296705 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0 16189.712128 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1 16233.649026 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu2 16482.290150 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu3 16023.322228 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu4 15783.091520 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu5 16494.569595 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu6 16447.404395 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu7 15759.743463 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 16180.712614 # average UpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0 32338.651654 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1 32798.575128 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2 32688.848524 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3 32493.922605 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu4 32762.870315 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu5 32434.027154 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu6 32938.201208 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu7 32550.617072 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 32626.453799 # average ReadExReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70669.375358 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69634.702247 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68785.934605 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69103.660787 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69682.085135 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70037.781204 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69224.799458 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70131.134864 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 69645.316542 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0 37392.456932 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1 37669.920319 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2 37618.199442 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3 37586.670253 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu4 37788.664827 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu5 37213.451661 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu6 37920.435535 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu7 37448.451945 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 37580.667094 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0 37392.456932 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1 37669.920319 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2 37618.199442 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3 37586.670253 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu4 37788.664827 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu5 37213.451661 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu6 37920.435535 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu7 37448.451945 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 37580.667094 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 19223 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 2973 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs 6.465859 # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.writebacks::writebacks 6255 # number of writebacks
|
|
system.l2c.writebacks::total 6255 # number of writebacks
|
|
system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits
|
|
system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits
|
|
system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::cpu6 5 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::cpu7 5 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::total 40 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu0 11 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu1 10 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu2 14 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu3 13 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu4 8 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu5 9 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu6 8 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu7 10 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::total 83 # number of ReadSharedReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0 13 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2 23 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3 16 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu4 15 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0 13 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2 23 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3 16 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu4 15 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 123 # number of overall MSHR hits
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 1242 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 1242 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0 2119 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1 2003 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2 2060 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3 2101 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu4 1934 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu5 2026 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu6 2138 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu7 2027 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 16408 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0 4594 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1 4668 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2 4632 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3 4558 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu4 4689 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu5 4672 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu6 4632 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu7 4646 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 37091 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0 687 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1 702 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu2 720 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu3 724 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu4 732 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu5 672 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu6 730 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu7 687 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 5654 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0 5281 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1 5370 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2 5352 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3 5282 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu4 5421 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu5 5344 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu6 5362 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu7 5333 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 42745 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0 5281 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1 5370 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2 5352 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3 5282 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu4 5421 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu5 5344 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu6 5362 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu7 5333 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 42745 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0 9743 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1 9811 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu2 9985 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu3 9849 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu4 9877 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu5 9910 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu6 9861 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu7 9739 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 78775 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0 5399 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1 5467 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu2 5427 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu3 5579 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu4 5520 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu5 5451 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu6 5590 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu7 5357 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 43790 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0 15142 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1 15278 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu2 15412 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu3 15428 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu4 15397 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu5 15361 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu6 15451 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu7 15096 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 122565 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 40841935 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 38564215 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 39647592 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 40417370 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 37145795 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 38899918 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 41229107 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 39009527 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 315755459 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0 102604763 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1 106353151 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2 105053935 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3 102451130 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu4 106647279 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu5 104810242 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu6 106228599 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu7 104763871 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 838912970 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 41984323 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 42028851 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42690563 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 43142020 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 43825891 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 40479162 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 43405339 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 41523836 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 339079985 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0 144589086 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1 148382002 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2 147744498 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3 145593150 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu4 150473170 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu5 145289404 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu6 149633938 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu7 146287707 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 1177992955 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0 144589086 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1 148382002 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2 147744498 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3 145593150 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu4 150473170 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu5 145289404 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu6 149633938 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu7 146287707 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 1177992955 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 506398152 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 509332752 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 518417832 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 511679337 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 512962712 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 514656758 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 512189388 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 505729590 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 4091366521 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0 506398152 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1 509332752 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2 518417832 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu3 511679337 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu4 512962712 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu5 514656758 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu6 512189388 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu7 505729590 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 4091366521 # number of overall MSHR uncacheable cycles
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886240 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.875820 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.881472 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882402 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.883508 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.877436 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.899075 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.885540 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.884004 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.709827 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.723497 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.718585 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.718587 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.720055 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.729544 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719255 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.719195 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.719808 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059373 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060154 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.062359 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.061649 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.063680 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.057584 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.062128 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.059713 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.060828 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0 0.292690 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1 0.296325 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2 0.297466 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3 0.292033 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu4 0.301050 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu5 0.295673 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu6 0.294777 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu7 0.296855 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.295854 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0 0.292690 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1 0.296325 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2 0.297466 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3 0.292033 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu4 0.301050 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu5 0.295673 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu6 0.294777 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu7 0.296855 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.295854 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19274.155262 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19253.227659 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19246.403883 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19237.206092 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19206.719235 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19200.354393 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19283.960243 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19244.956586 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19243.994332 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22334.515237 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22783.451371 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22680.037781 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22477.211496 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22744.141395 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22433.699058 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22933.635363 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22549.261946 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 22617.696207 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61112.551674 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59870.158120 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59292.448611 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59588.425414 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59871.435792 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60236.848214 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59459.368493 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60442.264920 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59971.698797 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0 27379.111153 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1 27631.657728 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2 27605.474215 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3 27564.019311 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu4 27757.456189 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu5 27187.388473 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu6 27906.366654 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu7 27430.659479 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 27558.613990 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0 27379.111153 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1 27631.657728 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2 27605.474215 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3 27564.019311 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu4 27757.456189 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu5 27187.388473 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu6 27906.366654 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu7 27430.659479 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 27558.613990 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51975.587807 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51914.458465 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51919.662694 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51952.415169 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51935.072593 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51933.073461 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51940.917554 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51928.287298 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51937.372529 # average ReadReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 33443.280412 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 33337.658856 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 33637.284713 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 33165.629829 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 33315.757096 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 33504.118091 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 33149.271115 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 33500.900238 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 33381.197903 # average overall mshr uncacheable latency
|
|
system.membus.trans_dist::ReadReq 78773 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 84410 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 43787 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 43783 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 6255 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 1278 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 61348 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 49073 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 3087 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 5646 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377440 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 377440 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1081783 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 1081783 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 56900 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 253448 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 253448 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 253448 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 289313112 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 57.8 # Layer utilization (%)
|
|
system.membus.respLayer0.occupancy 244976000 # Layer occupancy (ticks)
|
|
system.membus.respLayer0.utilization 49.0 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 662658 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 284136 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 332740 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 12293 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 5765 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 6528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 78775 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 371396 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 43790 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 43780 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 83926 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 105295 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 29475 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 29475 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 162920 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 162916 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 292639 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133502 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133647 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133520 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133779 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133528 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133790 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133396 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 1068709 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1800550 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1795691 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1783667 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1792707 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1790564 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791999 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1796631 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 14339895 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 335681 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 623777 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 1.148975 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.984758 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 172972 27.73% 27.73% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 258444 41.43% 69.16% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 133198 21.35% 90.52% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 46670 7.48% 98.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 10752 1.72% 99.72% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 1603 0.26% 99.98% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 135 0.02% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 623777 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 493769156 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 102470874 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 20.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 102502346 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 20.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 102645272 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 20.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 102492443 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 20.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 102725884 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 20.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 102549521 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 20.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 102424000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 20.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 102560017 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 20.5 # Layer utilization (%)
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---------- End Simulation Statistics ----------
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