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gem5/src/arch/arm
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Andreas Hansson d4273cc9a6 mem: Set the cache line size on a system level 
This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.

Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.

A follow-on patch updates the configuration scripts accordingly.
2013-07-18 08:31:16 -04:00
..
insts arm: set ldr_ret_uop as conditional or unconditional control 2013-04-17 16:07:10 -05:00
isa arm: Add support for the m5fail pseudo-op 2013-05-14 15:06:50 +02:00
linux arm: Enable support for triggering a sim panic on kernel panics 2013-04-22 13:20:31 -04:00
ArmInterrupts.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ArmISA.py arm: Make ID registers ISA parameters 2013-01-07 13:05:35 -05:00
ArmNativeTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ArmSystem.py arm: Enable support for triggering a sim panic on kernel panics 2013-04-22 13:20:31 -04:00
ArmTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
decoder.cc Decoder: Remove the thread context get/set from the decoder. 2013-01-04 19:00:45 -06:00
decoder.hh x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch 2013-01-22 00:10:10 -06:00
faults.cc scons: Add warning for missing field initializers 2013-02-19 05:56:06 -05:00
faults.hh SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. 2011-11-02 01:25:15 -07:00
interrupts.cc ARM: Implement ARM CPU interrupts 2010-06-02 12:58:16 -05:00
interrupts.hh arm: Add a method to query interrupt state ignoring CPSR masks 2013-04-22 13:20:32 -04:00
intregs.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
isa.cc mem: Set the cache line size on a system level 2013-07-18 08:31:16 -04:00
isa.hh scons: Add warning for overloaded virtual functions 2013-02-19 05:56:07 -05:00
isa_traits.hh ISA: generic Linux thread info support 2012-11-02 11:32:00 -05:00
kernel_stats.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
locked_mem.hh o3: Fix issue with LLSC ordering and speculation 2013-01-07 13:05:33 -05:00
microcode_rom.hh arm: include missing file for arm 2009-04-21 15:40:26 -07:00
miscregs.cc gem5: Fix a number of incorrect case statements 2012-05-10 18:04:26 -05:00
miscregs.hh arm: Remove the register mapping hack used when copying TCs 2013-01-07 13:05:44 -05:00
mmapped_ipr.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
nativetrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
nativetrace.hh ARM: Add vfpv3 support to native trace. 2011-05-04 20:38:26 -05:00
pagetable.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
process.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
process.hh scons: Add warning for overloaded virtual functions 2013-02-19 05:56:06 -05:00
registers.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
remote_gdb.cc ARM: Keep a copy of the fpscr len and stride fields in the decoder. 2013-01-04 18:09:35 -06:00
remote_gdb.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
SConscript arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
SConsopts arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
stacktrace.cc ARM: implement the ProcessInfo methods 2012-06-11 11:07:41 -04:00
stacktrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
system.cc arm: Make ID registers ISA parameters 2013-01-07 13:05:35 -05:00
system.hh ARM: Fix MPIDR and MIDR register implementation. 2012-06-05 01:23:10 -04:00
table_walker.cc arm: fix a page table walker issue where a page could be translated multiple times 2013-02-15 17:40:10 -05:00
table_walker.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
tlb.cc arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
tlb.hh arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
types.hh ARM: Fix issue with predicted next pc being wrong because of advance() ordering. 2012-06-29 11:18:28 -04:00
utility.cc arm: Remove the register mapping hack used when copying TCs 2013-01-07 13:05:44 -05:00
utility.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
vtophys.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
vtophys.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00