61d95de4c8
SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
215 lines
5.6 KiB
C++
215 lines
5.6 KiB
C++
//Todo: Update with statuses.
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//Need to handle delaying writes to the writeback bus if it's full at the
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//given time. Load store queue.
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#ifndef __CPU_BETA_CPU_SIMPLE_IEW_HH__
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#define __CPU_BETA_CPU_SIMPLE_IEW_HH__
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#include <queue>
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/beta_cpu/comm.hh"
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//Can IEW even stall? Space should be available/allocated already...maybe
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//if there's not enough write ports on the ROB or waiting for CDB
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//arbitration.
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template<class Impl>
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class SimpleIEW
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{
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private:
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//Typedefs from Impl
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typedef typename Impl::ISA ISA;
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typedef typename Impl::CPUPol CPUPol;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::Params Params;
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typedef typename CPUPol::IQ IQ;
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typedef typename CPUPol::RenameMap RenameMap;
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typedef typename CPUPol::LDSTQ LDSTQ;
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typedef typename CPUPol::TimeStruct TimeStruct;
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typedef typename CPUPol::IEWStruct IEWStruct;
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typedef typename CPUPol::RenameStruct RenameStruct;
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typedef typename CPUPol::IssueStruct IssueStruct;
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friend class Impl::FullCPU;
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public:
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enum Status {
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Running,
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Blocked,
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Idle,
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Squashing,
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Unblocking
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};
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private:
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Status _status;
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Status _issueStatus;
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Status _exeStatus;
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Status _wbStatus;
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public:
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class WritebackEvent : public Event {
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private:
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DynInstPtr inst;
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SimpleIEW<Impl> *iewStage;
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public:
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WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
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virtual void process();
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virtual const char *description();
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};
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public:
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SimpleIEW(Params ¶ms);
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void regStats();
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void setCPU(FullCPU *cpu_ptr);
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
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void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
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void setRenameMap(RenameMap *rm_ptr);
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void squash();
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void squashDueToBranch(DynInstPtr &inst);
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void squashDueToMem(DynInstPtr &inst);
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void block();
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inline void unblock();
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void wakeDependents(DynInstPtr &inst);
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void instToCommit(DynInstPtr &inst);
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private:
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void dispatchInsts();
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void executeInsts();
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public:
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void tick();
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void iew();
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//Interfaces to objects inside and outside of IEW.
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to get commit's output from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Wire to write information heading to previous stages. */
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typename TimeBuffer<TimeStruct>::wire toRename;
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/** Rename instruction queue interface. */
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TimeBuffer<RenameStruct> *renameQueue;
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/** Wire to get rename's output from rename queue. */
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typename TimeBuffer<RenameStruct>::wire fromRename;
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/** Issue stage queue. */
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TimeBuffer<IssueStruct> issueToExecQueue;
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/** Wire to read information from the issue stage time queue. */
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typename TimeBuffer<IssueStruct>::wire fromIssue;
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/**
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* IEW stage time buffer. Holds ROB indices of instructions that
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* can be marked as completed.
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*/
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TimeBuffer<IEWStruct> *iewQueue;
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/** Wire to write infromation heading to commit. */
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typename TimeBuffer<IEWStruct>::wire toCommit;
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//Will need internal queue to hold onto instructions coming from
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//the rename stage in case of a stall.
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/** Skid buffer between rename and IEW. */
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std::queue<RenameStruct> skidBuffer;
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protected:
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/** Instruction queue. */
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IQ instQueue;
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LDSTQ ldstQueue;
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#ifndef FULL_SYSTEM
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public:
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void lsqWriteback();
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#endif
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private:
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/** Pointer to rename map. Might not want this stage to directly
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* access this though...
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*/
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RenameMap *renameMap;
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/** CPU interface. */
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FullCPU *cpu;
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private:
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/** Commit to IEW delay, in ticks. */
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unsigned commitToIEWDelay;
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/** Rename to IEW delay, in ticks. */
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unsigned renameToIEWDelay;
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/**
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* Issue to execute delay, in ticks. What this actually represents is
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* the amount of time it takes for an instruction to wake up, be
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* scheduled, and sent to a FU for execution.
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*/
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unsigned issueToExecuteDelay;
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/** Width of issue's read path, in instructions. The read path is both
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* the skid buffer and the rename instruction queue.
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* Note to self: is this really different than issueWidth?
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*/
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unsigned issueReadWidth;
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/** Width of issue, in instructions. */
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unsigned issueWidth;
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/** Width of execute, in instructions. Might make more sense to break
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* down into FP vs int.
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*/
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unsigned executeWidth;
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/** Number of cycles stage has been squashing. Used so that the stage
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* knows when it can start unblocking, which is when the previous stage
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* has received the stall signal and clears up its outputs.
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*/
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unsigned cyclesSquashing;
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Stats::Scalar<> iewIdleCycles;
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Stats::Scalar<> iewSquashCycles;
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Stats::Scalar<> iewBlockCycles;
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Stats::Scalar<> iewUnblockCycles;
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// Stats::Scalar<> iewWBInsts;
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Stats::Scalar<> iewDispatchedInsts;
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Stats::Scalar<> iewDispSquashedInsts;
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Stats::Scalar<> iewDispLoadInsts;
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Stats::Scalar<> iewDispStoreInsts;
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Stats::Scalar<> iewDispNonSpecInsts;
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Stats::Scalar<> iewIQFullEvents;
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Stats::Scalar<> iewExecutedInsts;
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Stats::Scalar<> iewExecLoadInsts;
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Stats::Scalar<> iewExecStoreInsts;
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Stats::Scalar<> iewExecSquashedInsts;
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Stats::Scalar<> memOrderViolationEvents;
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Stats::Scalar<> predictedTakenIncorrect;
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};
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#endif // __CPU_BETA_CPU_IEW_HH__
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