61d95de4c8
SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
369 lines
9.9 KiB
C++
369 lines
9.9 KiB
C++
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#include "base/cprintf.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "mem/cache/cache.hh" // for dynamic cast
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/sim_events.hh"
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#include "sim/stats.hh"
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#include "cpu/beta_cpu/alpha_full_cpu.hh"
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#include "cpu/beta_cpu/alpha_params.hh"
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#include "cpu/beta_cpu/comm.hh"
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#ifdef FULL_SYSTEM
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#include "arch/alpha/osfpal.hh"
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#include "arch/alpha/isa_traits.hh"
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//#include "arch/alpha/ev5.hh"
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//using namespace EV5;
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#endif
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template <class Impl>
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AlphaFullCPU<Impl>::AlphaFullCPU(Params ¶ms)
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: FullBetaCPU<Impl>(params)
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{
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DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
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this->fetch.setCPU(this);
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this->decode.setCPU(this);
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this->rename.setCPU(this);
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this->iew.setCPU(this);
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this->commit.setCPU(this);
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this->rob.setCPU(this);
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::regStats()
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{
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// Register stats for everything that has stats.
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this->fullCPURegStats();
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this->fetch.regStats();
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this->decode.regStats();
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this->rename.regStats();
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this->iew.regStats();
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this->commit.regStats();
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}
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#ifndef FULL_SYSTEM
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// Will probably need to know which thread is calling syscall
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// Will need to pass that information in to the DynInst when it is constructed,
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// so that this call can be made with the proper thread number.
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template <class Impl>
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void
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AlphaFullCPU<Impl>::syscall(short thread_num)
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{
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DPRINTF(FullCPU, "AlphaFullCPU: Syscall() called.\n\n");
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// Commit stage needs to run as well.
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this->commit.tick();
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squashStages();
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// Temporarily increase this by one to account for the syscall
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// instruction.
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++(this->funcExeInst);
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// Copy over all important state to xc once all the unrolling is done.
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copyToXC();
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this->thread[0]->syscall();
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// this->thread[thread_num]->syscall();
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// Copy over all important state back to CPU.
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copyFromXC();
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// Decrease funcExeInst by one as the normal commit will handle
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// incrememnting it.
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--(this->funcExeInst);
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}
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// This is not a pretty function, and should only be used if it is necessary
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// to fake having everything squash all at once (ie for non-full system
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// syscalls). Maybe put this at the FullCPU level?
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template <class Impl>
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void
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AlphaFullCPU<Impl>::squashStages()
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{
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InstSeqNum rob_head = this->rob.readHeadSeqNum();
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// Now hack the time buffer to put this sequence number in the places
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// where the stages might read it.
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for (int i = 0; i < 5; ++i)
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{
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this->timeBuffer.access(-i)->commitInfo.doneSeqNum = rob_head;
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}
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this->fetch.squash(this->rob.readHeadNextPC());
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this->fetchQueue.advance();
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this->decode.squash();
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this->decodeQueue.advance();
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this->rename.squash();
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this->renameQueue.advance();
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this->renameQueue.advance();
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// Be sure to advance the IEW queues so that the commit stage doesn't
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// try to set an instruction as completed at the same time that it
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// might be deleting it.
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this->iew.squash();
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this->iewQueue.advance();
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this->iewQueue.advance();
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// Needs to tell the LSQ to write back all of its data
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this->iew.lsqWriteback();
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this->rob.squash(rob_head);
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this->commit.setSquashing();
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// Now hack the time buffer to clear the sequence numbers in the places
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// where the stages might read it.?
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for (int i = 0; i < 5; ++i)
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{
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this->timeBuffer.access(-i)->commitInfo.doneSeqNum = 0;
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}
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}
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#endif // FULL_SYSTEM
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template <class Impl>
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void
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AlphaFullCPU<Impl>::copyToXC()
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{
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
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{
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renamed_reg = this->renameMap.lookup(i);
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this->xc->regs.intRegFile[i] = this->regFile.readIntReg(renamed_reg);
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DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
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renamed_reg, this->regFile.intRegFile[renamed_reg]);
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
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{
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renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
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this->xc->regs.floatRegFile.d[i] =
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this->regFile.readFloatRegDouble(renamed_reg);
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this->xc->regs.floatRegFile.q[i] =
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this->regFile.readFloatRegInt(renamed_reg);
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}
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this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr;
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this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq;
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this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag;
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this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr;
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this->xc->regs.pc = this->rob.readHeadPC();
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this->xc->regs.npc = this->xc->regs.pc+4;
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this->xc->func_exe_inst = this->funcExeInst;
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}
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// This function will probably mess things up unless the ROB is empty and
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// there are no instructions in the pipeline.
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template <class Impl>
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void
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AlphaFullCPU<Impl>::copyFromXC()
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{
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
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{
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renamed_reg = this->renameMap.lookup(i);
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DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
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"now has data %lli.\n",
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renamed_reg, this->regFile.intRegFile[renamed_reg],
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this->xc->regs.intRegFile[i]);
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this->regFile.setIntReg(renamed_reg, this->xc->regs.intRegFile[i]);
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
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{
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renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
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this->regFile.setFloatRegDouble(renamed_reg,
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this->xc->regs.floatRegFile.d[i]);
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this->regFile.setFloatRegInt(renamed_reg,
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this->xc->regs.floatRegFile.q[i]);
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}
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// Then loop through the misc registers.
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this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr;
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this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq;
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this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag;
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this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr;
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// Then finally set the PC and the next PC.
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// regFile.pc = xc->regs.pc;
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// regFile.npc = xc->regs.npc;
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this->funcExeInst = this->xc->func_exe_inst;
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}
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#ifdef FULL_SYSTEM
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template <class Impl>
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uint64_t *
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AlphaFullCPU<Impl>::getIpr()
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{
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return this->regFile.getIpr();
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}
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template <class Impl>
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uint64_t
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AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
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{
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return this->regFile.readIpr(idx, fault);
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}
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template <class Impl>
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Fault
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AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
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{
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return this->regFile.setIpr(idx, val);
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}
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template <class Impl>
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int
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AlphaFullCPU<Impl>::readIntrFlag()
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{
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return this->regFile.readIntrFlag();
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::setIntrFlag(int val)
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{
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this->regFile.setIntrFlag(val);
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}
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// Can force commit stage to squash and stuff.
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template <class Impl>
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Fault
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AlphaFullCPU<Impl>::hwrei()
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{
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uint64_t *ipr = getIpr();
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if (!inPalMode())
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return Unimplemented_Opcode_Fault;
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setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
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// kernelStats.hwrei();
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if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
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// AlphaISA::swap_palshadow(®s, false);
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this->checkInterrupts = true;
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// FIXME: XXX check for interrupts? XXX
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return No_Fault;
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}
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template <class Impl>
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bool
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AlphaFullCPU<Impl>::simPalCheck(int palFunc)
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{
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// kernelStats.callpal(palFunc);
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switch (palFunc) {
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case PAL::halt:
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halt();
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if (--System::numSystemsRunning == 0)
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new SimExitEvent("all cpus halted");
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break;
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case PAL::bpt:
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case PAL::bugchk:
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if (this->system->breakpoint())
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return false;
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break;
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}
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return true;
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}
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// Probably shouldn't be able to switch to the trap handler as quickly as
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// this. Also needs to get the exception restart address from the commit
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// stage.
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template <class Impl>
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void
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AlphaFullCPU<Impl>::trap(Fault fault)
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{
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// Keep in mind that a trap may be initiated by fetch if there's a TLB
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// miss
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uint64_t PC = this->commit.readCommitPC();
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DPRINTF(Fault, "Fault %s\n", FaultName(fault));
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this->recordEvent(csprintf("Fault %s", FaultName(fault)));
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// kernelStats.fault(fault);
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if (fault == Arithmetic_Fault)
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panic("Arithmetic traps are unimplemented!");
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typename AlphaISA::InternalProcReg *ipr = getIpr();
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// exception restart address - Get the commit PC
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if (fault != Interrupt_Fault || !inPalMode(PC))
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ipr[AlphaISA::IPR_EXC_ADDR] = PC;
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if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
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fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
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// traps... skip faulting instruction
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ipr[AlphaISA::IPR_EXC_ADDR] += 4;
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}
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if (!inPalMode(PC))
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swapPALShadow(true);
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this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
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AlphaISA::fault_addr[fault] );
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this->regFile.setNextPC(PC + sizeof(MachInst));
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::processInterrupts()
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{
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// Check for interrupts here. For now can copy the code that exists
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// within isa_fullsys_traits.hh.
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}
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// swap_palshadow swaps in the values of the shadow registers and
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// swaps them with the values of the physical registers that map to the
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// same logical index.
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template <class Impl>
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void
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AlphaFullCPU<Impl>::swapPALShadow(bool use_shadow)
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{
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if (palShadowEnabled == use_shadow)
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panic("swap_palshadow: wrong PAL shadow state");
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palShadowEnabled = use_shadow;
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// Will have to lookup in rename map to get physical registers, then
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// swap.
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/*
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for (int i = 0; i < AlphaISA::NumIntRegs; i++) {
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if (reg_redir[i]) {
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AlphaISA::IntReg temp = regs->intRegFile[i];
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regs->intRegFile[i] = regs->palregs[i];
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regs->palregs[i] = temp;
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}
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}
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*/
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}
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#endif // FULL_SYSTEM
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