c8538d6a7e
python/m5/config.py:
- Enhanced Proxy class now supports subscripting, e.g.,
parent.cpu[0] or even parent.cpu[0].icache.
- Proxy also supports multiplication (e.g., parent.cycle * 3),
though this feature has not been tested.
- Subscript 0 works even on non-lists, so you can safely say
cpu[0] and get the first cpu even if there's only one.
- Changed name of proxy object from 'Super' to 'parent', and
changed "wild card" notation from plain 'Super' to 'parent.any'.
python/m5/objects/AlphaConsole.mpy:
python/m5/objects/BaseCPU.mpy:
python/m5/objects/BaseSystem.mpy:
python/m5/objects/Device.mpy:
python/m5/objects/Ethernet.mpy:
python/m5/objects/Ide.mpy:
python/m5/objects/IntrControl.mpy:
python/m5/objects/Pci.mpy:
python/m5/objects/PhysicalMemory.mpy:
python/m5/objects/Platform.mpy:
python/m5/objects/SimConsole.mpy:
python/m5/objects/SimpleDisk.mpy:
python/m5/objects/Tsunami.mpy:
python/m5/objects/Uart.mpy:
Change 'Super.foo' to 'parent.foo' (and 'Super' to 'parent.any').
--HG--
extra : convert_revision : f996d0a3366d5e3e60ae5973691148c3d7cd497d
51 lines
2.2 KiB
Text
51 lines
2.2 KiB
Text
from Device import FooPioDevice, DmaDevice
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simobj PciConfigData(SimObject):
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type = 'PciConfigData'
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VendorID = Param.UInt16("Vendor ID")
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DeviceID = Param.UInt16("Device ID")
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Command = Param.UInt16(0, "Command")
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Status = Param.UInt16(0, "Status")
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Revision = Param.UInt8(0, "Device")
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ProgIF = Param.UInt8(0, "Programming Interface")
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SubClassCode = Param.UInt8(0, "Sub-Class Code")
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ClassCode = Param.UInt8(0, "Class Code")
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CacheLineSize = Param.UInt8(0, "System Cacheline Size")
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LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
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HeaderType = Param.UInt8(0, "PCI Header Type")
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BIST = Param.UInt8(0, "Built In Self Test")
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BAR0 = Param.UInt32(0x00, "Base Address Register 0")
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BAR1 = Param.UInt32(0x00, "Base Address Register 1")
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BAR2 = Param.UInt32(0x00, "Base Address Register 2")
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BAR3 = Param.UInt32(0x00, "Base Address Register 3")
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BAR4 = Param.UInt32(0x00, "Base Address Register 4")
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BAR5 = Param.UInt32(0x00, "Base Address Register 5")
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BAR0Size = Param.UInt32(0, "Base Address Register 0 Size")
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BAR1Size = Param.UInt32(0, "Base Address Register 1 Size")
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BAR2Size = Param.UInt32(0, "Base Address Register 2 Size")
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BAR3Size = Param.UInt32(0, "Base Address Register 3 Size")
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BAR4Size = Param.UInt32(0, "Base Address Register 4 Size")
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BAR5Size = Param.UInt32(0, "Base Address Register 5 Size")
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CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
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SubsystemID = Param.UInt16(0x00, "Subsystem ID")
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SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
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ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
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InterruptLine = Param.UInt8(0x00, "Interrupt Line")
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InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
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MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
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MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
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simobj PciConfigAll(FooPioDevice):
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type = 'PciConfigAll'
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simobj PciDevice(DmaDevice):
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type = 'PciDevice'
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abstract = True
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addr = 0xffffffffL
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pci_bus = Param.Int("PCI bus")
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pci_dev = Param.Int("PCI device number")
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pci_func = Param.Int("PCI function code")
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configdata = Param.PciConfigData(parent.any, "PCI Config data")
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configspace = Param.PciConfigAll(parent.any, "PCI Configspace")
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