3ece6ab029
wierd ini files. The ini files are still used as an intermediate step,
but a sophisticated python library exists to help build them more
easily.
SConscript:
add the new embedded file stuff
remove all of the old object description junk
base/inifile.cc:
base/inifile.hh:
get rid of findDefault and findAppend since they were the source
of much evil.
base/trace.cc:
For now, if we don't have the dprintf_stream set up, dump
to standard out. We probably want a command line option
for this.
dev/alpha_console.cc:
PioDevice now takes a platform parameter.
All PioDevices must have a pio_latency parameter. We stick
a dummy parameter in here for now until we get rid of the
builder stuff.
dev/alpha_console.hh:
don't need Platform anymore
dev/baddev.cc:
PioDevice now takes a platform parameter.
All PioDevices must have a pio_latency parameter. We stick
a dummy parameter in here for now until we get rid of the
builder stuff. Same for the platform parameter, though we just
pass the PioDevice a null parameter since it isn't used by
this device and it's quicker.
dev/baddev.hh:
fix #include guards
dev/etherlink.cc:
rename parameters.
dev/ethertap.cc:
rename parameters
dev/ide_ctrl.cc:
All devices need an address even if it will get overwritten later.
dev/ide_disk.cc:
use an enum for the drive ID stuff.
rename disk_delay -> delay
Actually, I think that we should implement "cable select" and
have the controller tell the drive what it is.
dev/io_device.cc:
dev/io_device.hh:
All IO devices take a Platform *
dev/ns_gige.cc:
all devices need an io_bus. rename header_bus to io_bus
We don't need stuff for the interrupt controller since
it's all in the platform now.
dev/ns_gige.hh:
We don't need stuff for the interrupt controller now since
it's all in the platform.
dev/pciconfigall.cc:
Pass a dummy NULL to the PioDevice for the platform since
we don't need one.
dev/pcidev.cc:
Move a bunch of common functionality into the PciDev
dev/platform.hh:
remove unneeded code
dev/tsunami.cc:
remove unused param
dev/tsunami_cchip.cc:
pass platform pointer
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
pass platform variable
dev/uart.hh:
don't need to keep a platform pointer. it's in the base class
kern/linux/linux_system.cc:
kern/tru64/tru64_system.cc:
rename some parameters
sim/builder.cc:
clean up builder code. use more parameters from the
config node. all sections with a type= are now created,
the old mechanisms no longer work
sim/builder.hh:
remove some extra variables since they are found in the ConfigNode
sim/main.cc:
add a quick hack command line argument -X to dump out the
embedded files. (probably should be fixed up a little.)
accept .mpy files
printing to the streams has to happen after the hierarchy
is built since we're moving away from param contexts
sim/param.cc:
add parsing support for ranges
sim/process.cc:
isValid isn't very useful anymore. interpret the names
stdout, stderr, cout, cerr for the file descriptors
sim/pyconfig/SConscript:
Add Action handlers for creating an embedded python file
and for creating an embedded C file.
use these action handlers to embed all objects found in the objects
tree into the binary along with the importer and the m5config stuff
sim/pyconfig/m5config.py:
Major changes to the original configuration file generator. These
changes largely involve implementing copy-on-write like semantics
for all of the SimObjects. Real documentation must be written.
sim/universe.cc:
Universe becomes a SimObject since we don't really have the notion of
param contexts in the python code.
--HG--
rename : sim/pyconfig/m5configbase.py => sim/pyconfig/m5config.py
extra : convert_revision : c353453e5beb91c37f15755998fc0d8858c6829a
360 lines
12 KiB
C++
360 lines
12 KiB
C++
/*
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* Copyright (c) 2001-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* System Console Definition
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*/
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#include <cstddef>
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#include <cstdio>
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#include <string>
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#include "base/inifile.hh"
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#include "base/str.hh" // for to_number()
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#include "base/trace.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "dev/alpha_console.hh"
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#include "dev/simconsole.hh"
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#include "dev/simple_disk.hh"
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#include "dev/tlaser_clock.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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#include "dev/tsunami_io.hh"
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#include "sim/sim_object.hh"
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#include "targetarch/byte_swap.hh"
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using namespace std;
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AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
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System *system, BaseCPU *cpu, Platform *p,
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int num_cpus, MemoryController *mmu, Addr a,
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HierParams *hier, Bus *bus)
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: PioDevice(name, p), disk(d), console(cons), addr(a)
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&AlphaConsole::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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}
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alphaAccess = new AlphaAccess;
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alphaAccess->last_offset = size - 1;
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alphaAccess->kernStart = system->getKernelStart();
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alphaAccess->kernEnd = system->getKernelEnd();
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alphaAccess->entryPoint = system->getKernelEntry();
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alphaAccess->version = ALPHA_ACCESS_VERSION;
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alphaAccess->numCPUs = num_cpus;
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alphaAccess->mem_size = system->physmem->size();
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alphaAccess->cpuClock = cpu->getFreq() / 1000000;
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alphaAccess->intrClockFrequency = platform->intrFrequency();
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alphaAccess->diskUnit = 1;
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alphaAccess->diskCount = 0;
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alphaAccess->diskPAddr = 0;
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alphaAccess->diskBlock = 0;
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alphaAccess->diskOperation = 0;
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alphaAccess->outputChar = 0;
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alphaAccess->inputChar = 0;
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alphaAccess->bootStrapImpure = 0;
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alphaAccess->bootStrapCPU = 0;
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alphaAccess->align2 = 0;
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}
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Fault
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AlphaConsole::read(MemReqPtr &req, uint8_t *data)
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{
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memset(data, 0, req->size);
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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switch (req->size)
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{
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case sizeof(uint32_t):
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *(uint32_t*)data);
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switch (daddr)
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{
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case offsetof(AlphaAccess, last_offset):
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*(uint32_t*)data = alphaAccess->last_offset;
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break;
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case offsetof(AlphaAccess, version):
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*(uint32_t*)data = alphaAccess->version;
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break;
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case offsetof(AlphaAccess, numCPUs):
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*(uint32_t*)data = alphaAccess->numCPUs;
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break;
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case offsetof(AlphaAccess, bootStrapCPU):
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*(uint32_t*)data = alphaAccess->bootStrapCPU;
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break;
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case offsetof(AlphaAccess, intrClockFrequency):
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*(uint32_t*)data = alphaAccess->intrClockFrequency;
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break;
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default:
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// Old console code read in everyting as a 32bit int
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*(uint32_t*)data = *(uint32_t*)(consoleData + daddr);
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}
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break;
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case sizeof(uint64_t):
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *(uint64_t*)data);
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switch (daddr)
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{
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case offsetof(AlphaAccess, inputChar):
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*(uint64_t*)data = console->console_in();
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break;
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case offsetof(AlphaAccess, cpuClock):
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*(uint64_t*)data = alphaAccess->cpuClock;
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break;
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case offsetof(AlphaAccess, mem_size):
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*(uint64_t*)data = alphaAccess->mem_size;
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break;
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case offsetof(AlphaAccess, kernStart):
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*(uint64_t*)data = alphaAccess->kernStart;
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break;
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case offsetof(AlphaAccess, kernEnd):
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*(uint64_t*)data = alphaAccess->kernEnd;
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break;
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case offsetof(AlphaAccess, entryPoint):
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*(uint64_t*)data = alphaAccess->entryPoint;
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break;
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case offsetof(AlphaAccess, diskUnit):
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*(uint64_t*)data = alphaAccess->diskUnit;
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break;
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case offsetof(AlphaAccess, diskCount):
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*(uint64_t*)data = alphaAccess->diskCount;
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break;
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case offsetof(AlphaAccess, diskPAddr):
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*(uint64_t*)data = alphaAccess->diskPAddr;
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break;
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case offsetof(AlphaAccess, diskBlock):
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*(uint64_t*)data = alphaAccess->diskBlock;
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break;
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case offsetof(AlphaAccess, diskOperation):
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*(uint64_t*)data = alphaAccess->diskOperation;
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break;
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case offsetof(AlphaAccess, outputChar):
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*(uint64_t*)data = alphaAccess->outputChar;
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break;
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case offsetof(AlphaAccess, bootStrapImpure):
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*(uint64_t*)data = alphaAccess->bootStrapImpure;
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break;
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default:
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panic("Unknown 64bit access, %#x\n", daddr);
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}
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break;
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default:
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return Machine_Check_Fault;
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}
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return No_Fault;
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}
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Fault
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AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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{
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uint64_t val;
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switch (req->size) {
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case sizeof(uint32_t):
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val = *(uint32_t *)data;
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break;
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case sizeof(uint64_t):
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val = *(uint64_t *)data;
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break;
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default:
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return Machine_Check_Fault;
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}
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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ExecContext *other_xc;
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switch (daddr) {
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case offsetof(AlphaAccess, diskUnit):
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alphaAccess->diskUnit = val;
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break;
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case offsetof(AlphaAccess, diskCount):
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alphaAccess->diskCount = val;
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break;
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case offsetof(AlphaAccess, diskPAddr):
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alphaAccess->diskPAddr = val;
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break;
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case offsetof(AlphaAccess, diskBlock):
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alphaAccess->diskBlock = val;
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break;
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case offsetof(AlphaAccess, diskOperation):
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if (val == 0x13)
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disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
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alphaAccess->diskCount);
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else
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panic("Invalid disk operation!");
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break;
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case offsetof(AlphaAccess, outputChar):
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console->out((char)(val & 0xff));
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break;
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case offsetof(AlphaAccess, bootStrapImpure):
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alphaAccess->bootStrapImpure = val;
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break;
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case offsetof(AlphaAccess, bootStrapCPU):
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warn("%d: Trying to launch another CPU!", curTick);
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assert(val > 0 && "Must not access primary cpu");
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other_xc = req->xc->system->execContexts[val];
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other_xc->regs.intRegFile[16] = val;
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other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
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other_xc->regs.intRegFile[0] = val;
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other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
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other_xc->activate(); //Start the cpu
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break;
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default:
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return Machine_Check_Fault;
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}
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return No_Fault;
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}
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Tick
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AlphaConsole::cacheAccess(MemReqPtr &req)
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{
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return curTick + 1000;
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}
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void
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AlphaAccess::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(last_offset);
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SERIALIZE_SCALAR(version);
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SERIALIZE_SCALAR(numCPUs);
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SERIALIZE_SCALAR(mem_size);
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SERIALIZE_SCALAR(cpuClock);
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SERIALIZE_SCALAR(intrClockFrequency);
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SERIALIZE_SCALAR(kernStart);
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SERIALIZE_SCALAR(kernEnd);
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SERIALIZE_SCALAR(entryPoint);
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SERIALIZE_SCALAR(diskUnit);
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SERIALIZE_SCALAR(diskCount);
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SERIALIZE_SCALAR(diskPAddr);
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SERIALIZE_SCALAR(diskBlock);
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SERIALIZE_SCALAR(diskOperation);
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SERIALIZE_SCALAR(outputChar);
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SERIALIZE_SCALAR(inputChar);
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SERIALIZE_SCALAR(bootStrapImpure);
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SERIALIZE_SCALAR(bootStrapCPU);
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}
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void
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AlphaAccess::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(last_offset);
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UNSERIALIZE_SCALAR(version);
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UNSERIALIZE_SCALAR(numCPUs);
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UNSERIALIZE_SCALAR(mem_size);
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UNSERIALIZE_SCALAR(cpuClock);
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UNSERIALIZE_SCALAR(intrClockFrequency);
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UNSERIALIZE_SCALAR(kernStart);
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UNSERIALIZE_SCALAR(kernEnd);
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UNSERIALIZE_SCALAR(entryPoint);
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UNSERIALIZE_SCALAR(diskUnit);
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UNSERIALIZE_SCALAR(diskCount);
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UNSERIALIZE_SCALAR(diskPAddr);
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UNSERIALIZE_SCALAR(diskBlock);
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UNSERIALIZE_SCALAR(diskOperation);
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UNSERIALIZE_SCALAR(outputChar);
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UNSERIALIZE_SCALAR(inputChar);
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UNSERIALIZE_SCALAR(bootStrapImpure);
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UNSERIALIZE_SCALAR(bootStrapCPU);
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}
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void
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AlphaConsole::serialize(ostream &os)
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{
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alphaAccess->serialize(os);
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}
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void
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AlphaConsole::unserialize(Checkpoint *cp, const std::string §ion)
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{
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alphaAccess->unserialize(cp, section);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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SimObjectParam<SimConsole *> sim_console;
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SimObjectParam<SimpleDisk *> disk;
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Param<int> num_cpus;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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SimObjectParam<System *> system;
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SimObjectParam<BaseCPU *> cpu;
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SimObjectParam<Platform *> platform;
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SimObjectParam<Bus*> io_bus;
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Param<Tick> pio_latency;
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SimObjectParam<HierParams *> hier;
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END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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INIT_PARAM(sim_console, "The Simulator Console"),
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INIT_PARAM(disk, "Simple Disk"),
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INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(system, "system object"),
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INIT_PARAM(cpu, "Processor"),
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INIT_PARAM(platform, "platform"),
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INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
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INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
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END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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CREATE_SIM_OBJECT(AlphaConsole)
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{
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return new AlphaConsole(getInstanceName(), sim_console, disk,
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system, cpu, platform, num_cpus, mmu,
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addr, hier, io_bus);
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}
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REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
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