612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
104 lines
3.9 KiB
C++
104 lines
3.9 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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* Stephen Hines
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*/
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#include <string>
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#include "arch/arm/faults.hh"
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#include "arch/arm/table_walker.hh"
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#include "arch/arm/tlb.hh"
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#include "arch/arm/vtophys.hh"
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#include "base/chunk_generator.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "mem/fs_translating_port_proxy.hh"
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using namespace std;
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using namespace ArmISA;
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Addr
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ArmISA::vtophys(Addr vaddr)
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{
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fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
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}
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Addr
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ArmISA::vtophys(ThreadContext *tc, Addr addr)
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{
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Fault fault;
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// Set up a functional memory Request to pass to the TLB
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// to get it to translate the vaddr to a paddr
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Request req(0, addr, 64, 0x40, -1, 0, 0, 0);
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ArmISA::TLB *tlb;
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// Check the TLBs for a translation
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// It's possible that there is a valid translation in the tlb
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// that is no loger valid in the page table in memory
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// so we need to check here first
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//
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// Calling translateFunctional invokes a table-walk if required
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// so we should always succeed
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tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
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fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
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if (fault == NoFault)
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return req.getPaddr();
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tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
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fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
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if (fault == NoFault)
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return req.getPaddr();
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panic("Table walkers support functional accesses. We should never get here\n");
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}
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bool
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ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
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{
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if (vtophys(tc, vaddr) != -1)
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return true;
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return false;
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}
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