612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
146 lines
5.4 KiB
C++
Executable file
146 lines
5.4 KiB
C++
Executable file
/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Thomas Grocutt
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*/
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#include "arch/arm/faults.hh"
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#include "arch/arm/stage2_mmu.hh"
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#include "arch/arm/system.hh"
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#include "arch/arm/tlb.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Checkpoint.hh"
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#include "debug/TLB.hh"
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#include "debug/TLBVerbose.hh"
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using namespace ArmISA;
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Stage2MMU::Stage2MMU(const Params *p)
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: SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb)
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{
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stage1Tlb()->setMMU(this);
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stage2Tlb()->setMMU(this);
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}
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Fault
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Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
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uint8_t *data, int numBytes, Request::Flags flags, int masterId,
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bool isFunctional)
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{
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Fault fault;
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// translate to physical address using the second stage MMU
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Request req = Request();
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req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
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if (isFunctional) {
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fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read);
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} else {
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fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read);
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}
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// Now do the access.
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if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) {
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Packet pkt = Packet(&req, MemCmd::ReadReq);
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pkt.dataStatic(data);
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if (isFunctional) {
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stage1Tlb()->getWalkerPort().sendFunctional(&pkt);
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} else {
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stage1Tlb()->getWalkerPort().sendAtomic(&pkt);
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}
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assert(!pkt.isError());
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}
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// If there was a fault annotate it with the flag saying the foult occured
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// while doing a translation for a stage 1 page table walk.
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if (fault != NoFault) {
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ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
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armFault->annotate(ArmFault::S1PTW, true);
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armFault->annotate(ArmFault::OVA, oVAddr);
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}
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return fault;
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}
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Fault
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Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr,
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Stage2Translation *translation, int numBytes, Request::Flags flags,
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int masterId)
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{
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Fault fault;
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// translate to physical address using the second stage MMU
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translation->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId);
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fault = translation->translateTiming(tc);
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return fault;
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}
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Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
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uint8_t *_data, Event *_event, Addr _oVAddr)
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: data(_data), event(_event), parent(_parent), oVAddr(_oVAddr),
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fault(NoFault)
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{
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}
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void
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Stage2MMU::Stage2Translation::finish(Fault _fault, RequestPtr req, ThreadContext *tc,
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BaseTLB::Mode mode)
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{
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fault = _fault;
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// If there was a fault annotate it with the flag saying the foult occured
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// while doing a translation for a stage 1 page table walk.
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if (fault != NoFault) {
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ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
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armFault->annotate(ArmFault::S1PTW, true);
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armFault->annotate(ArmFault::OVA, oVAddr);
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}
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if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
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DmaPort& port = parent.stage1Tlb()->getWalkerPort();
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port.dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes,
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event, data, tc->getCpuPtr()->clockPeriod(),
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req->getFlags());
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} else {
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// We can't do the DMA access as there's been a problem, so tell the
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// event we're done
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event->process();
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}
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}
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ArmISA::Stage2MMU *
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ArmStage2MMUParams::create()
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{
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return new ArmISA::Stage2MMU(this);
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}
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