612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
557 lines
18 KiB
C++
557 lines
18 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010-2013 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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def template MrsDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
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%(BasicExecDeclare)s
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};
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}};
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def template MrsConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template MrsBankedRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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uint8_t byteMask;
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bool r;
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
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uint8_t _sysM, bool _r);
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%(BasicExecDeclare)s
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};
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}};
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def template MrsBankedRegConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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uint8_t _sysM,
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bool _r)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest),
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byteMask(_sysM), r(_r)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template MsrBankedRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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bool r;
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
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uint8_t _sysM, bool _r);
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%(BasicExecDeclare)s
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};
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}};
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def template MsrBankedRegConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _op1,
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uint8_t _sysM,
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bool _r)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _sysM),
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r(_r)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template MsrRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
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%(BasicExecDeclare)s
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};
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}};
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def template MsrRegConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _op1,
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uint8_t mask)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template MsrImmDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
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%(BasicExecDeclare)s
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};
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}};
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def template MsrImmConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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uint32_t imm,
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uint8_t mask)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template MrrcOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
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IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm);
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%(BasicExecDeclare)s
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};
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}};
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def template MrrcOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex op1,
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IntRegIndex dest,
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IntRegIndex dest2,
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uint32_t imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, dest,
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dest2, imm)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template McrrOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2,
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IntRegIndex _dest, uint32_t imm);
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%(BasicExecDeclare)s
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};
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}};
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def template McrrOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex op1,
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IntRegIndex op2,
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IntRegIndex dest,
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uint32_t imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2,
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dest, imm)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template ImmOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, uint64_t _imm);
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%(BasicExecDeclare)s
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};
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}};
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def template ImmOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template RegImmOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
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%(BasicExecDeclare)s
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};
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}};
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def template RegImmOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, uint64_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template RegRegOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1);
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%(BasicExecDeclare)s
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};
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}};
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def template RegRegOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template RegRegRegImmOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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uint64_t _imm);
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%(BasicExecDeclare)s
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};
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}};
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def template RegRegRegImmOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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IntRegIndex _op2,
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uint64_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _op2, _imm)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template RegRegRegRegOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1,
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IntRegIndex _op2, IntRegIndex _op3);
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%(BasicExecDeclare)s
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};
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}};
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def template RegRegRegRegOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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IntRegIndex _op2,
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IntRegIndex _op3)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _op2, _op3)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template RegRegRegOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
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%(BasicExecDeclare)s
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};
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}};
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def template RegRegRegOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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IntRegIndex _op2)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _op2)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template RegRegImmOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1,
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uint64_t _imm);
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%(BasicExecDeclare)s
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};
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}};
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def template RegRegImmOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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uint64_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _imm)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template RegImmImmOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2);
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%(BasicExecDeclare)s
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};
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}};
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def template RegImmImmOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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uint64_t _imm1,
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uint64_t _imm2)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _imm1, _imm2)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template RegRegImmImmOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1,
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uint64_t _imm1, uint64_t _imm2);
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%(BasicExecDeclare)s
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};
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}};
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def template RegRegImmImmOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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uint64_t _imm1,
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uint64_t _imm2)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _imm1, _imm2)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
}
|
|
}};
|
|
|
|
def template RegImmRegOpDeclare {{
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
protected:
|
|
public:
|
|
// Constructor
|
|
%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1);
|
|
%(BasicExecDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template RegImmRegOpConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest,
|
|
uint64_t _imm,
|
|
IntRegIndex _op1)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
_dest, _imm, _op1)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
}
|
|
}};
|
|
|
|
def template RegImmRegShiftOpDeclare {{
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
protected:
|
|
public:
|
|
// Constructor
|
|
%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
|
|
int32_t _shiftAmt, ArmShiftType _shiftType);
|
|
%(BasicExecDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template RegImmRegShiftOpConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest,
|
|
uint64_t _imm,
|
|
IntRegIndex _op1,
|
|
int32_t _shiftAmt,
|
|
ArmShiftType _shiftType)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
_dest, _imm, _op1, _shiftAmt, _shiftType)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
}
|
|
}};
|
|
|