612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
256 lines
8.5 KiB
C++
256 lines
8.5 KiB
C++
/*
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* Copyright (c) 2011-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_INSTS_DATA64_HH__
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#define __ARCH_ARM_INSTS_DATA64_HH__
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#include "arch/arm/insts/static_inst.hh"
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#include "base/trace.hh"
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namespace ArmISA
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{
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class DataXImmOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1;
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uint64_t imm;
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DataXImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
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ArmStaticInst(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataXImmOnlyOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest;
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uint64_t imm;
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DataXImmOnlyOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, uint64_t _imm) :
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ArmStaticInst(mnem, _machInst, __opClass),
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dest(_dest), imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataXSRegOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1, op2;
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int32_t shiftAmt;
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ArmShiftType shiftType;
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DataXSRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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int32_t _shiftAmt, ArmShiftType _shiftType) :
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ArmStaticInst(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2),
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shiftAmt(_shiftAmt), shiftType(_shiftType)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataXERegOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1, op2;
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ArmExtendType extendType;
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int32_t shiftAmt;
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DataXERegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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ArmExtendType _extendType, int32_t _shiftAmt) :
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ArmStaticInst(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2),
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extendType(_extendType), shiftAmt(_shiftAmt)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataX1RegOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1;
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DataX1RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1) :
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ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataX1RegImmOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1;
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uint64_t imm;
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DataX1RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
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ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1),
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imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataX1Reg2ImmOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1;
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uint64_t imm1, imm2;
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DataX1Reg2ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1,
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uint64_t _imm2) :
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ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1),
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imm1(_imm1), imm2(_imm2)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataX2RegOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1, op2;
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DataX2RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
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ArmStaticInst(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataX2RegImmOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1, op2;
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uint64_t imm;
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DataX2RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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uint64_t _imm) :
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ArmStaticInst(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2), imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataX3RegOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1, op2, op3;
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DataX3RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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IntRegIndex _op3) :
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ArmStaticInst(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2), op3(_op3)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataXCondCompImmOp : public ArmStaticInst
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{
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protected:
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IntRegIndex op1;
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uint64_t imm;
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ConditionCode condCode;
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uint8_t defCc;
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DataXCondCompImmOp(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _op1, uint64_t _imm,
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ConditionCode _condCode, uint8_t _defCc) :
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ArmStaticInst(mnem, _machInst, __opClass),
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op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataXCondCompRegOp : public ArmStaticInst
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{
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protected:
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IntRegIndex op1, op2;
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ConditionCode condCode;
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uint8_t defCc;
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DataXCondCompRegOp(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2,
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ConditionCode _condCode, uint8_t _defCc) :
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ArmStaticInst(mnem, _machInst, __opClass),
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op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataXCondSelOp : public ArmStaticInst
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{
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protected:
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IntRegIndex dest, op1, op2;
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ConditionCode condCode;
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DataXCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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ConditionCode _condCode) :
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ArmStaticInst(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}
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#endif //__ARCH_ARM_INSTS_PREDINST_HH__
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