612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
204 lines
5.9 KiB
C++
204 lines
5.9 KiB
C++
/*
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* Copyright (c) 2011-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/arm/insts/data64.hh"
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namespace ArmISA
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{
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std::string
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DataXImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
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INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
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return ss.str();
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}
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std::string
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DataXImmOnlyOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, dest);
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ccprintf(ss, ", #%d", imm);
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return ss.str();
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}
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std::string
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DataXSRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
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op2, INTREG_ZERO, shiftAmt, shiftType, 0);
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return ss.str();
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}
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std::string
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DataXERegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
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op2, INTREG_ZERO, shiftAmt, LSL, 0);
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return ss.str();
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}
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std::string
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DataX1RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, dest);
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ccprintf(ss, ", ");
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printReg(ss, op1);
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return ss.str();
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}
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std::string
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DataX1RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, dest);
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ccprintf(ss, ", ");
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printReg(ss, op1);
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ccprintf(ss, ", #%d", imm);
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return ss.str();
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}
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std::string
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DataX1Reg2ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, dest);
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ccprintf(ss, ", ");
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printReg(ss, op1);
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ccprintf(ss, ", #%d, #%d", imm1, imm2);
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return ss.str();
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}
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std::string
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DataX2RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, dest);
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ccprintf(ss, ", ");
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printReg(ss, op1);
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ccprintf(ss, ", ");
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printReg(ss, op2);
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return ss.str();
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}
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std::string
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DataX2RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, dest);
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ccprintf(ss, ", ");
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printReg(ss, op1);
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ccprintf(ss, ", ");
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printReg(ss, op2);
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ccprintf(ss, ", #%d", imm);
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return ss.str();
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}
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std::string
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DataX3RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, dest);
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ccprintf(ss, ", ");
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printReg(ss, op1);
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ccprintf(ss, ", ");
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printReg(ss, op2);
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ccprintf(ss, ", ");
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printReg(ss, op3);
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return ss.str();
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}
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std::string
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DataXCondCompImmOp::generateDisassembly(
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Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, op1);
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ccprintf(ss, ", #%d, #%d", imm, defCc);
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ccprintf(ss, ", ");
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printCondition(ss, condCode, true);
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return ss.str();
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}
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std::string
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DataXCondCompRegOp::generateDisassembly(
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Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, op1);
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ccprintf(ss, ", ");
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printReg(ss, op2);
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ccprintf(ss, ", #%d", defCc);
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ccprintf(ss, ", ");
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printCondition(ss, condCode, true);
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return ss.str();
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}
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std::string
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DataXCondSelOp::generateDisassembly(
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Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printReg(ss, dest);
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ccprintf(ss, ", ");
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printReg(ss, op1);
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ccprintf(ss, ", ");
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printReg(ss, op2);
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ccprintf(ss, ", ");
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printCondition(ss, condCode, true);
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return ss.str();
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}
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}
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