612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
87 lines
3.6 KiB
Python
87 lines
3.6 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2009, 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from MemObject import MemObject
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# Basic stage 1 translation objects
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class ArmTableWalker(MemObject):
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type = 'ArmTableWalker'
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cxx_class = 'ArmISA::TableWalker'
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cxx_header = "arch/arm/table_walker.hh"
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is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
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port = MasterPort("Port for TableWalker to do walk the translation with")
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sys = Param.System(Parent.any, "system object parameter")
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num_squash_per_cycle = Param.Unsigned(2,
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"Number of outstanding walks that can be squashed per cycle")
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class ArmTLB(SimObject):
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type = 'ArmTLB'
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cxx_class = 'ArmISA::TLB'
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cxx_header = "arch/arm/tlb.hh"
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size = Param.Int(64, "TLB size")
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walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
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is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
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# Stage 2 translation objects, only used when virtualisation is being used
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class ArmStage2TableWalker(ArmTableWalker):
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is_stage2 = True
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class ArmStage2TLB(ArmTLB):
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size = 32
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walker = ArmStage2TableWalker()
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is_stage2 = True
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class ArmStage2MMU(SimObject):
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type = 'ArmStage2MMU'
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cxx_class = 'ArmISA::Stage2MMU'
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cxx_header = 'arch/arm/stage2_mmu.hh'
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tlb = Param.ArmTLB("Stage 1 TLB")
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stage2_tlb = Param.ArmTLB("Stage 2 TLB")
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class ArmStage2IMMU(ArmStage2MMU):
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tlb = Parent.itb
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stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker())
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class ArmStage2DMMU(ArmStage2MMU):
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tlb = Parent.dtb
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stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker())
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