48863a1a43
makes it easier to implement PCI device models.
dev/pcidev.cc:
default implementations for read/write and readBarX/writeBarX functions
--HG--
extra : convert_revision : bbe2e2a2a506e2dd94d98f8e0feaefef96380be9
296 lines
9 KiB
C++
296 lines
9 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Interface for devices using PCI configuration
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*/
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#ifndef __DEV_PCIDEV_HH__
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#define __DEV_PCIDEV_HH__
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#include "dev/io_device.hh"
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#include "dev/pcireg.h"
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#include "dev/platform.hh"
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#define BAR_IO_MASK 0x3
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#define BAR_MEM_MASK 0xF
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#define BAR_IO_SPACE_BIT 0x1
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#define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT)
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#define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
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class PciConfigAll;
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class MemoryController;
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/**
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* This class encapulates the first 64 bytes of a singles PCI
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* devices config space that in configured by the configuration file.
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*/
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class PciConfigData : public SimObject
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{
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public:
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/**
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* Constructor to initialize the devices config space to 0.
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*/
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PciConfigData(const std::string &name)
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: SimObject(name)
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{
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memset(config.data, 0, sizeof(config.data));
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memset(BARAddrs, 0, sizeof(BARAddrs));
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memset(BARSize, 0, sizeof(BARSize));
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}
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/** The first 64 bytes */
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PCIConfig config;
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/** The size of the BARs */
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uint32_t BARSize[6];
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/** The addresses of the BARs */
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Addr BARAddrs[6];
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};
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/**
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* PCI device, base implemnation is only config space.
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* Each device is connected to a PCIConfigSpace device
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* which returns -1 for everything but the pcidevs that
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* register with it. This object registers with the PCIConfig space
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* object.
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*/
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class PciDev : public DmaDevice
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{
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public:
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struct Params
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{
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std::string name;
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Platform *plat;
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MemoryController *mmu;
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/**
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* A pointer to the configspace all object that calls us when
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* a read comes to this particular device/function.
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*/
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PciConfigAll *configSpace;
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/**
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* A pointer to the object that contains the first 64 bytes of
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* config space
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*/
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PciConfigData *configData;
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/** The bus number we are on */
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uint32_t busNum;
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/** The device number we have */
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uint32_t deviceNum;
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/** The function number */
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uint32_t functionNum;
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};
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protected:
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Params *_params;
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public:
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const Params *params() const { return _params; }
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protected:
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/** The current config space. Unlike the PciConfigData this is
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* updated during simulation while continues to reflect what was
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* in the config file.
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*/
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PCIConfig config;
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/** The size of the BARs */
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uint32_t BARSize[6];
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/** The current address mapping of the BARs */
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Addr BARAddrs[6];
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bool
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isBAR(Addr addr, int bar) const
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{
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assert(bar >= 0 && bar < 6);
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return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar];
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}
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int
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getBAR(Addr addr)
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{
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for (int i = 0; i <= 5; ++i)
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if (isBAR(addr, i))
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return i;
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return -1;
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}
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bool
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getBAR(Addr paddr, Addr &daddr, int &bar)
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{
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int b = getBAR(paddr);
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if (b < 0)
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return false;
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daddr = paddr - BARAddrs[b];
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bar = b;
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return true;
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}
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protected:
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Platform *plat;
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PciConfigData *configData;
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public:
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Addr pciToDma(Addr pciAddr) const
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{ return plat->pciToDma(pciAddr); }
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void
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intrPost()
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{ plat->postPciInt(configData->config.interruptLine); }
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void
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intrClear()
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{ plat->clearPciInt(configData->config.interruptLine); }
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uint8_t
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interruptLine()
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{ return configData->config.interruptLine; }
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public:
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/**
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* Constructor for PCI Dev. This function copies data from the
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* config file object PCIConfigData and registers the device with
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* a PciConfigAll object.
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*/
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PciDev(Params *params);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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public:
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/**
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* Implement the read/write as BAR accesses
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*/
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Fault readBar(MemReqPtr &req, uint8_t *data);
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Fault writeBar(MemReqPtr &req, const uint8_t *data);
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public:
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/**
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* Read from a specific BAR
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*/
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virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
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virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
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virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
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virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
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virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
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virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
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public:
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/**
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* Write to a specific BAR
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*/
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virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
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virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
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virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
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virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
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virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
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virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
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public:
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/**
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* Write to the PCI config space data that is stored locally. This may be
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* overridden by the device but at some point it will eventually call this
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* for normal operations that it does not need to override.
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* @param offset the offset into config space
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* @param size the size of the write
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* @param data the data to write
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*/
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virtual void writeConfig(int offset, int size, const uint8_t* data);
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/**
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* Read from the PCI config space data that is stored locally. This may be
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* overridden by the device but at some point it will eventually call this
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* for normal operations that it does not need to override.
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* @param offset the offset into config space
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* @param size the size of the read
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* @param data pointer to the location where the read value should be stored
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*/
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virtual void readConfig(int offset, int size, uint8_t *data);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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inline Fault
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PciDev::readBar(MemReqPtr &req, uint8_t *data)
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{
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if (isBAR(req->paddr, 0))
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return readBar0(req, req->paddr - BARAddrs[0], data);
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if (isBAR(req->paddr, 1))
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return readBar1(req, req->paddr - BARAddrs[1], data);
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if (isBAR(req->paddr, 2))
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return readBar2(req, req->paddr - BARAddrs[2], data);
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if (isBAR(req->paddr, 3))
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return readBar3(req, req->paddr - BARAddrs[3], data);
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if (isBAR(req->paddr, 4))
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return readBar4(req, req->paddr - BARAddrs[4], data);
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if (isBAR(req->paddr, 5))
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return readBar5(req, req->paddr - BARAddrs[5], data);
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return Machine_Check_Fault;
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}
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inline Fault
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PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
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{
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if (isBAR(req->paddr, 0))
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return writeBar0(req, req->paddr - BARAddrs[0], data);
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if (isBAR(req->paddr, 1))
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return writeBar1(req, req->paddr - BARAddrs[1], data);
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if (isBAR(req->paddr, 2))
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return writeBar2(req, req->paddr - BARAddrs[2], data);
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if (isBAR(req->paddr, 3))
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return writeBar3(req, req->paddr - BARAddrs[3], data);
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if (isBAR(req->paddr, 4))
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return writeBar4(req, req->paddr - BARAddrs[4], data);
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if (isBAR(req->paddr, 5))
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return writeBar5(req, req->paddr - BARAddrs[5], data);
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return Machine_Check_Fault;
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}
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#endif // __DEV_PCIDEV_HH__
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