c761aaae65
objects. The improper serialization of arrays was particularly
bad.
dev/alpha_console.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
the pio interface is a different simobject and should have a
different name.
dev/ethertap.cc:
fix serialization.
dev/ide_ctrl.cc:
- the pio interface is a different simobject and should have a
different name.
- properly initialize variables
- When serializing an array, the size is the number of elements,
not the number of bytes!
dev/pcidev.cc:
When serializing an array, the size is the number of elements,
not the number of bytes!
dev/tsunami_io.hh:
Don't make objects SimObjects if they're not exposed to python.
Don't add serialization functions to events, it's generally not
what you want.
allow the real time clock and interval timer to serialize themselves,
must pass a base name since it is not a SimObject and the values will
be going into the section of the parent.
--HG--
extra : convert_revision : 3fc5de9b858ed770c8f385cf38b53242cf859c33
140 lines
4.3 KiB
C++
140 lines
4.3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Isa Fake Device implementation
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/isa_fake.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
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HierParams *hier, Bus *bus, Addr size)
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: PioDevice(name, NULL), addr(a)
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (bus) {
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pioInterface = newPioInterface(name + ".pio", hier, bus, this,
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&IsaFake::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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}
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}
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Fault
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IsaFake::read(MemReqPtr &req, uint8_t *data)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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#if TRACING_ON
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
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#endif
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switch (req->size) {
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case sizeof(uint64_t):
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*(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL;
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return No_Fault;
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case sizeof(uint32_t):
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*(uint32_t*)data = 0xFFFFFFFF;
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return No_Fault;
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case sizeof(uint16_t):
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*(uint16_t*)data = 0xFFFF;
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return No_Fault;
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case sizeof(uint8_t):
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*(uint8_t*)data = 0xFF;
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return No_Fault;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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DPRINTFN("Isa FakeSMC ERROR: read daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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Fault
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IsaFake::write(MemReqPtr &req, const uint8_t *data)
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{
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DPRINTF(Tsunami, "write - va=%#x size=%d \n",
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req->vaddr, req->size);
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//:Addr daddr = (req->paddr & addr_mask) >> 6;
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return No_Fault;
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}
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Tick
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IsaFake::cacheAccess(MemReqPtr &req)
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{
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return curTick;
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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SimObjectParam<Bus*> io_bus;
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Param<Tick> pio_latency;
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SimObjectParam<HierParams *> hier;
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Param<Addr> size;
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END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
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BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
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INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
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INIT_PARAM_DFLT(size, "Size of address range", 0x8)
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END_INIT_SIM_OBJECT_PARAMS(IsaFake)
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CREATE_SIM_OBJECT(IsaFake)
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{
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return new IsaFake(getInstanceName(), addr, mmu, hier, io_bus, size);
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}
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REGISTER_SIM_OBJECT("IsaFake", IsaFake)
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