54227f9e57
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
684 lines
78 KiB
Text
684 lines
78 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000010 # Number of seconds simulated
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sim_ticks 10412000 # Number of ticks simulated
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final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 40558 # Simulator instruction rate (inst/s)
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host_op_rate 50593 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 91854675 # Simulator tick rate (ticks/s)
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host_mem_usage 232720 # Number of bytes of host memory used
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host_seconds 0.11 # Real time elapsed on the host
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sim_insts 4596 # Number of instructions simulated
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sim_ops 5734 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25600 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 400 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 13 # Number of system calls
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system.cpu.numCycles 20825 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 2492 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 2432 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 2229 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 47 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 8838 # Type of FU issued
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system.cpu.iq.rate 0.424394 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 221 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3246 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1415 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1167 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.404994 # Inst execution rate
|
|
system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 7997 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 3850 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 7766 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 4596 # Number of instructions committed
|
|
system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 2140 # Number of memory references committed
|
|
system.cpu.commit.loads 1201 # Number of loads committed
|
|
system.cpu.commit.membars 12 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1008 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 4980 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 22290 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 23328 # The number of ROB writes
|
|
system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 4596 # Number of Instructions Simulated
|
|
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
|
|
system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 38756 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 7886 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 15116 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
|
|
system.cpu.icache.replacements 3 # number of replacements
|
|
system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 1564 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1564 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 368 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2306 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 502 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3549000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3549000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1700000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1700000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5249000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 5249000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5249000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 5249000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055409 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055409 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.052350 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.052350 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33800 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33800 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40476.190476 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40476.190476 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 188.003042 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 37 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.103352 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 141.702568 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 46.300474 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004324 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001413 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005737 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 37 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 364 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 406 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 406 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10097000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3413000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 13510000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1657000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1657000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 10097000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 5070000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 15167000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 10097000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 5070000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 15167000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942568 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.907731 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942568 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.916479 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942568 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.916479 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36189.964158 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40152.941176 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 37115.384615 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39452.380952 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39452.380952 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 37357.142857 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 37357.142857 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9207000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12243500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9207000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4564000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 13771000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9207000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|