Andreas Hansson 5ea60a95b3 config: Adjust DRAM channel interleaving defaults ... This patch changes the DRAM channel interleaving default behaviour to be more representative. The default address mapping (RoRaBaCoCh) moves the channel bits towards the least significant bits, and uses 128 byte as the default channel interleaving granularity. These defaults can be overridden if desired, but should serve as a sensible starting point for most use-cases.		2015-02-03 14:25:52 -05:00
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Benchmarks.py	arm, tests: Update config files to more recent kernels and create 64-bit regressions.	2014-10-29 23:18:27 -05:00
CacheConfig.py	config: Add --memchecker option	2014-12-23 09:31:18 -05:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	scons: Do not build the InOrderCPU	2015-01-20 08:12:45 -05:00
FSConfig.py	config: arm: fix os_flags	2015-01-30 15:49:34 -06:00
MemConfig.py	config: Adjust DRAM channel interleaving defaults	2015-02-03 14:25:52 -05:00
O3_ARM_v7a.py	cpu: Change writeback modeling for outstanding instructions	2014-09-03 07:42:33 -04:00
Options.py	config: Expose the DRAM ranks as a command-line option	2014-12-23 09:31:18 -05:00
Simulation.py	config: Add options to take/resume from SimPoint checkpoints	2014-12-23 09:31:17 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00