284 lines
7.6 KiB
C++
284 lines
7.6 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Korey Sewell
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* Jaidev Patwardhan
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*/
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#ifndef __MIPS_FAULTS_HH__
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#define __MIPS_FAULTS_HH__
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#include "arch/mips/pra_constants.hh"
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#include "cpu/thread_context.hh"
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#include "debug/MipsPRA.hh"
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#include "sim/faults.hh"
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namespace MipsISA
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{
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typedef const Addr FaultVect;
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class MipsFaultBase : public FaultBase
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{
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protected:
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virtual bool skipFaultingInstruction() {return false;}
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virtual bool setRestartAddress() {return true;}
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public:
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struct FaultVals
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{
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const FaultName name;
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const FaultVect vect;
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};
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
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{}
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void setHandlerPC(Addr, ThreadContext *);
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#endif
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void setExceptionState(ThreadContext *, uint8_t);
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};
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template <typename T>
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class MipsFault : public MipsFaultBase
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{
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protected:
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static FaultVals vals;
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public:
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FaultName name() const { return vals.name; }
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FaultVect vect() const { return vals.vect; }
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};
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template <typename T>
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class AddressFault : public MipsFault<T>
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{
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protected:
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Addr vaddr;
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bool store;
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AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
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{}
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};
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template <typename T>
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class TlbFault : public AddressFault<T>
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{
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protected:
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Addr asid;
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Addr vpn;
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TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) :
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AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn)
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{}
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void
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setTlbExceptionState(ThreadContext *tc, uint8_t excCode)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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this->setExceptionState(tc, excCode);
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
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EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
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entryHi.asid = this->asid;
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entryHi.vpn2 = this->vpn >> 2;
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entryHi.vpn2x = this->vpn & 0x3;
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tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
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ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
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context.badVPN2 = this->vpn >> 2;
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tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
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}
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};
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class MachineCheckFault : public MipsFault<MachineCheckFault>
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{
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public:
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bool isMachineCheckFault() {return true;}
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};
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static inline Fault genMachineCheckFault()
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{
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return new MachineCheckFault;
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}
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class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
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{
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public:
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bool isNonMaskableInterrupt() {return true;}
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};
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class AddressErrorFault : public AddressFault<AddressErrorFault>
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{
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public:
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AddressErrorFault(Addr _vaddr, bool _store) :
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AddressFault<AddressErrorFault>(_vaddr, _store)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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class ResetFault : public MipsFault<ResetFault>
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{
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public:
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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class SystemCallFault : public MipsFault<SystemCallFault>
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{
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public:
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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class SoftResetFault : public MipsFault<SoftResetFault>
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{
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public:
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
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{
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protected:
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int coProcID;
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public:
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CoprocessorUnusableFault(int _procid) : coProcID(_procid)
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{}
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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class ReservedInstructionFault : public MipsFault<ReservedInstructionFault>
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{
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public:
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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class ThreadFault : public MipsFault<ThreadFault>
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{
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public:
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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class IntegerOverflowFault : public MipsFault<IntegerOverflowFault>
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{
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protected:
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bool skipFaultingInstruction() {return true;}
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public:
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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class InterruptFault : public MipsFault<InterruptFault>
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{
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protected:
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bool setRestartAddress() {return false;}
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public:
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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class TrapFault : public MipsFault<TrapFault>
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{
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public:
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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class BreakpointFault : public MipsFault<BreakpointFault>
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{
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public:
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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class TlbRefillFault : public TlbFault<TlbRefillFault>
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{
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public:
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TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
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TlbFault<TlbRefillFault>(asid, vaddr, vpn, store)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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class TlbInvalidFault : public TlbFault<TlbInvalidFault>
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{
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public:
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TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
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TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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class TlbModifiedFault : public TlbFault<TlbModifiedFault>
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{
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public:
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TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) :
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TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
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{
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public:
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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} // namespace MipsISA
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#endif // __MIPS_FAULTS_HH__
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