4ed184eade
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge. --HG-- rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc rename : cpu/thread_state.hh => src/cpu/thread_state.hh rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : sim/eventq.hh => src/sim/eventq.hh rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh rename : sim/serialize.cc => src/sim/serialize.cc rename : sim/stat_control.cc => src/sim/stat_control.cc rename : sim/stat_control.hh => src/sim/stat_control.hh rename : sim/system.hh => src/sim/system.hh extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
225 lines
5.6 KiB
C
225 lines
5.6 KiB
C
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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*/
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "m5op.h"
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char *progname;
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void
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usage()
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{
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printf("usage: m5 ivlb <interval>\n"
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" m5 ivle <interval>\n"
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" m5 initparam\n"
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" m5 sw99param\n"
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" m5 exit [delay]\n"
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" m5 resetstats [delay [period]]\n"
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" m5 dumpstats [delay [period]]\n"
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" m5 dumpresetstats [delay [period]]\n"
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" m5 checkpoint [delay [period]]\n"
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" m5 readfile\n"
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"\n"
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"All times in nanoseconds!\n");
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exit(1);
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}
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#define COMPARE(X) (strcmp(X, command) == 0)
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int
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main(int argc, char *argv[])
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{
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char *command;
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uint64_t param;
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uint64_t arg1 = 0;
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uint64_t arg2 = 0;
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progname = argv[0];
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if (argc < 2)
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usage();
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command = argv[1];
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if (COMPARE("ivlb")) {
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if (argc != 3)
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usage();
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arg1 = strtoul(argv[2], NULL, 0);
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m5_ivlb(arg1);
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return 0;
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}
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if (COMPARE("ivle")) {
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if (argc != 3)
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usage();
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arg1 = strtoul(argv[2], NULL, 0);
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m5_ivle(arg1);
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return 0;
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}
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if (COMPARE("initparam")) {
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if (argc != 2)
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usage();
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printf("%ld", m5_initparam());
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return 0;
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}
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if (COMPARE("sw99param")) {
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if (argc != 2)
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usage();
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param = m5_initparam();
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// run-time, rampup-time, rampdown-time, warmup-time, connections
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printf("%d %d %d %d %d", (param >> 48) & 0xfff,
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(param >> 36) & 0xfff, (param >> 24) & 0xfff,
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(param >> 12) & 0xfff, (param >> 0) & 0xfff);
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return 0;
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}
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if (COMPARE("exit")) {
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switch (argc) {
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case 3:
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arg1 = strtoul(argv[2], NULL, 0);
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case 2:
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m5_exit(arg1);
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return 0;
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default:
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usage();
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}
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}
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if (COMPARE("resetstats")) {
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switch (argc) {
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case 4:
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arg2 = strtoul(argv[3], NULL, 0);
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case 3:
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arg1 = strtoul(argv[2], NULL, 0);
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case 2:
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m5_reset_stats(arg1, arg2);
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return 0;
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default:
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usage();
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}
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}
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if (COMPARE("dumpstats")) {
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switch (argc) {
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case 4:
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arg2 = strtoul(argv[3], NULL, 0);
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case 3:
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arg1 = strtoul(argv[2], NULL, 0);
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case 2:
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m5_dump_stats(arg1, arg2);
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return 0;
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default:
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usage();
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}
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}
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if (COMPARE("dumpresetstats")) {
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switch (argc) {
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case 4:
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arg2 = strtoul(argv[3], NULL, 0);
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case 3:
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arg1 = strtoul(argv[2], NULL, 0);
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case 2:
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m5_dumpreset_stats(arg1, arg2);
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return 0;
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default:
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usage();
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}
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}
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if (COMPARE("readfile")) {
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char buf[256*1024];
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int offset = 0;
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int len;
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if (argc != 2)
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usage();
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while ((len = m5_readfile(buf, sizeof(buf), offset)) > 0) {
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write(STDOUT_FILENO, buf, len);
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offset += len;
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}
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return 0;
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}
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if (COMPARE("checkpoint")) {
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switch (argc) {
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case 4:
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arg2 = strtoul(argv[3], NULL, 0);
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case 3:
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arg1 = strtoul(argv[2], NULL, 0);
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case 2:
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m5_checkpoint(arg1, arg2);
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return 0;
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default:
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usage();
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}
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return 0;
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}
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if (COMPARE("loadsymbol")) {
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m5_loadsymbol(arg1);
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return 0;
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if (COMPARE("readfile")) {
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char buf[256*1024];
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int offset = 0;
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int len;
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if (argc != 2)
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usage();
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while ((len = m5_readfile(buf, sizeof(buf), offset)) > 0) {
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write(STDOUT_FILENO, buf, len);
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offset += len;
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}
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return 0;
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}
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usage();
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}
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