arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/fake_syscall.cc: arch/alpha/faults.cc: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/circlebuf.cc: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/cprintf.cc: base/cprintf.hh: base/fast_alloc.cc: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/exec_aout.h: base/loader/exec_ecoff.h: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/pollevent.cc: base/pollevent.hh: base/random.cc: base/random.hh: base/range.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/statistics.cc: base/statistics.hh: base/str.cc: base/trace.cc: base/trace.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/console.cc: dev/console.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/simple_disk.cc: dev/simple_disk.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: sim/debug.cc: sim/eventq.cc: sim/eventq.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/prog.cc: sim/prog.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_object.cc: sim/sim_object.hh: sim/sim_time.cc: sim/system.cc: sim/system.hh: sim/universe.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/tap/tap.cc: Make include paths explicit. --HG-- extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
104 lines
2.6 KiB
C++
104 lines
2.6 KiB
C++
/* $Id$ */
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#ifndef __EV5_H__
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#define __EV5_H__
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#ifndef SYSTEM_EV5
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#error This code is only valid for EV5 systems
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#endif
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#include "targetarch/isa_traits.hh"
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void m5_exit();
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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#define MODE2MASK(X) (1 << (X))
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// Alpha IPR register accessors
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#define PC_PAL(X) ((X) & 0x1)
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#define MCSR_SP(X) (((X) >> 1) & 0x3)
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#define ICSR_SDE(X) (((X) >> 30) & 0x1)
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#define ICSR_SPE(X) (((X) >> 28) & 0x3)
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#define ICSR_FPE(X) (((X) >> 26) & 0x1)
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#define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
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#define DTB_CM_CM(X) (((X) >> 3) & 0x3)
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#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
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#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
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#define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
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#define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
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#define DTB_PTE_FONW(X) (((X) >> 2) & 0x1)
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#define DTB_PTE_GH(X) (((X) >> 5) & 0x3)
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#define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
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#define ICM_CM(X) (((X) >> 3) & 0x3)
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#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
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#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
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#define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
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#define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
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#define ITB_PTE_GH(X) (((X) >> 5) & 0x3)
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#define ITB_PTE_ASMA(X) (((X) >> 4) & 0x1)
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#define VA_UNIMPL_MASK ULL(0xfffff80000000000)
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#define VA_IMPL_MASK ULL(0x000007ffffffffff)
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#define VA_IMPL(X) ((X) & VA_IMPL_MASK)
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#define VA_VPN(X) (VA_IMPL(X) >> 13)
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#define VA_SPACE(X) (((X) >> 41) & 0x3)
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#define VA_POFS(X) ((X) & 0x1fff)
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#define PA_IMPL_MASK ULL(0xffffffffff)
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#define PA_UNCACHED_BIT ULL(0x8000000000)
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#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000))
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#define PA_PFN2PA(X) ((X) << 13)
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#define MM_STAT_BAD_VA_MASK 0x0020
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#define MM_STAT_DTB_MISS_MASK 0x0010
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#define MM_STAT_FONW_MASK 0x0008
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#define MM_STAT_FONR_MASK 0x0004
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#define MM_STAT_ACV_MASK 0x0002
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#define MM_STAT_WR_MASK 0x0001
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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// VPTE size for HW_LD/HW_ST
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#define HW_VPTE ((inst >> 11) & 0x1)
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// QWORD size for HW_LD/HW_ST
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#define HW_QWORD ((inst >> 12) & 0x1)
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// ALT mode for HW_LD/HW_ST
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#define HW_ALT (((inst >> 14) & 0x1) ? ALTMODE : 0)
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// LOCK/COND mode for HW_LD/HW_ST
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#define HW_LOCK (((inst >> 10) & 0x1) ? LOCKED : 0)
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#define HW_COND (((inst >> 10) & 0x1) ? LOCKED : 0)
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// PHY size for HW_LD/HW_ST
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#define HW_PHY (((inst >> 15) & 0x1) ? PHYSICAL : 0)
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// OFFSET for HW_LD/HW_ST
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#define HW_OFS (inst & 0x3ff)
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#define PAL_BASE 0x4000
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#endif //__EV5_H__
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