5df96cb690
This patch cleans up the packet memory allocation confusion. The data is always allocated at the requesting side, when a packet is created (or copied), and there is never a need for any device to allocate any space if it is merely responding to a paket. This behaviour is in line with how SystemC and TLM works as well, thus increasing interoperability, and matching established conventions. The redundant calls to Packet::allocate are removed, and the checks in the function are tightened up to make sure data is only ever allocated once. There are still some oddities in the packet copy constructor where we copy the data pointer if it is static (without ownership), and allocate new space if the data is dynamic (with ownership). The latter is being worked on further in a follow-on patch.
338 lines
11 KiB
C++
338 lines
11 KiB
C++
/*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/** @file
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* Implements a 8250 UART
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*/
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "debug/Uart.hh"
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#include "dev/platform.hh"
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#include "dev/terminal.hh"
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#include "dev/uart8250.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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using namespace std;
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using namespace TheISA;
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Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
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: uart(u)
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{
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DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
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intrBit = bit;
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}
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const char *
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Uart8250::IntrEvent::description() const
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{
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return "uart interrupt delay";
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}
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void
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Uart8250::IntrEvent::process()
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{
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if (intrBit & uart->IER) {
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DPRINTF(Uart, "UART InterEvent, interrupting\n");
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uart->platform->postConsoleInt();
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uart->status |= intrBit;
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uart->lastTxInt = curTick();
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}
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else
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DPRINTF(Uart, "UART InterEvent, not interrupting\n");
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}
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/* The linux serial driver (8250.c about line 1182) loops reading from
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* the device until the device reports it has no more data to
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* read. After a maximum of 255 iterations the code prints "serial8250
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* too much work for irq X," and breaks out of the loop. Since the
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* simulated system is so much slower than the actual system, if a
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* user is typing on the keyboard it is very easy for them to provide
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* input at a fast enough rate to not allow the loop to exit and thus
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* the error to be printed. This magic number provides a delay between
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* the time the UART receives a character to send to the simulated
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* system and the time it actually notifies the system it has a
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* character to send to alleviate this problem. --Ali
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*/
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void
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Uart8250::IntrEvent::scheduleIntr()
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{
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static const Tick interval = 225 * SimClock::Int::ns;
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DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
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curTick() + interval);
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if (!scheduled())
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uart->schedule(this, curTick() + interval);
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else
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uart->reschedule(this, curTick() + interval);
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}
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Uart8250::Uart8250(const Params *p)
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: Uart(p, 8), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
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txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
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{
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}
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Tick
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Uart8250::read(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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assert(pkt->getSize() == 1);
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Addr daddr = pkt->getAddr() - pioAddr;
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DPRINTF(Uart, " read register %#x\n", daddr);
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // read byte
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if (term->dataAvailable())
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pkt->set(term->in());
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else {
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pkt->set((uint8_t)0);
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// A limited amount of these are ok.
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DPRINTF(Uart, "empty read of RX register\n");
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}
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status &= ~RX_INT;
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platform->clearConsoleInt();
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if (term->dataAvailable() && (IER & UART_IER_RDI))
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rxIntrEvent.scheduleIntr();
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} else { // dll divisor latch
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;
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}
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break;
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case 0x1:
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if (!(LCR & 0x80)) { // Intr Enable Register(IER)
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pkt->set(IER);
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} else { // DLM divisor latch MSB
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;
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}
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break;
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case 0x2: // Intr Identification Register (IIR)
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DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
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if (status & RX_INT) /* Rx data interrupt has a higher priority */
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pkt->set(IIR_RXID);
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else if (status & TX_INT) {
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pkt->set(IIR_TXID);
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//Tx interrupts are cleared on IIR reads
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status &= ~TX_INT;
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} else
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pkt->set(IIR_NOPEND);
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break;
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case 0x3: // Line Control Register (LCR)
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pkt->set(LCR);
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break;
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case 0x4: // Modem Control Register (MCR)
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pkt->set(MCR);
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break;
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case 0x5: // Line Status Register (LSR)
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uint8_t lsr;
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lsr = 0;
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// check if there are any bytes to be read
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if (term->dataAvailable())
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lsr = UART_LSR_DR;
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lsr |= UART_LSR_TEMT | UART_LSR_THRE;
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pkt->set(lsr);
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break;
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case 0x6: // Modem Status Register (MSR)
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pkt->set((uint8_t)0);
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break;
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case 0x7: // Scratch Register (SCR)
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pkt->set((uint8_t)0); // doesn't exist with at 8250.
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break;
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default:
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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/* uint32_t d32 = *data;
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DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
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*/
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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Uart8250::write(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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assert(pkt->getSize() == 1);
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Addr daddr = pkt->getAddr() - pioAddr;
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DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get<uint8_t>());
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // write byte
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term->out(pkt->get<uint8_t>());
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platform->clearConsoleInt();
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status &= ~TX_INT;
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if (UART_IER_THRI & IER)
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txIntrEvent.scheduleIntr();
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} else { // dll divisor latch
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;
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}
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break;
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case 0x1:
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if (!(LCR & 0x80)) { // Intr Enable Register(IER)
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IER = pkt->get<uint8_t>();
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if (UART_IER_THRI & IER)
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{
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DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
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if (curTick() - lastTxInt > 225 * SimClock::Int::ns) {
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DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
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curTick(), lastTxInt);
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txIntrEvent.process();
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} else {
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DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n",
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curTick(), lastTxInt);
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txIntrEvent.scheduleIntr();
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}
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}
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else
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{
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DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
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if (txIntrEvent.scheduled())
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deschedule(txIntrEvent);
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if (status & TX_INT)
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platform->clearConsoleInt();
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status &= ~TX_INT;
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}
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if ((UART_IER_RDI & IER) && term->dataAvailable()) {
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DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
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rxIntrEvent.scheduleIntr();
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} else {
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DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
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if (rxIntrEvent.scheduled())
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deschedule(rxIntrEvent);
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if (status & RX_INT)
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platform->clearConsoleInt();
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status &= ~RX_INT;
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}
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} else { // DLM divisor latch MSB
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;
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}
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break;
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case 0x2: // FIFO Control Register (FCR)
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break;
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case 0x3: // Line Control Register (LCR)
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LCR = pkt->get<uint8_t>();
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break;
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case 0x4: // Modem Control Register (MCR)
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if (pkt->get<uint8_t>() == (UART_MCR_LOOP | 0x0A))
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MCR = 0x9A;
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break;
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case 0x7: // Scratch Register (SCR)
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// We are emulating a 8250 so we don't have a scratch reg
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break;
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default:
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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void
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Uart8250::dataAvailable()
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{
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// if the kernel wants an interrupt when we have data
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if (IER & UART_IER_RDI)
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{
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platform->postConsoleInt();
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status |= RX_INT;
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}
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}
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AddrRangeList
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Uart8250::getAddrRanges() const
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{
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AddrRangeList ranges;
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ranges.push_back(RangeSize(pioAddr, pioSize));
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return ranges;
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}
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void
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Uart8250::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(status);
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SERIALIZE_SCALAR(IER);
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SERIALIZE_SCALAR(DLAB);
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SERIALIZE_SCALAR(LCR);
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SERIALIZE_SCALAR(MCR);
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Tick rxintrwhen;
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if (rxIntrEvent.scheduled())
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rxintrwhen = rxIntrEvent.when();
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else
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rxintrwhen = 0;
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Tick txintrwhen;
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if (txIntrEvent.scheduled())
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txintrwhen = txIntrEvent.when();
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else
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txintrwhen = 0;
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SERIALIZE_SCALAR(rxintrwhen);
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SERIALIZE_SCALAR(txintrwhen);
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}
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void
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Uart8250::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(status);
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UNSERIALIZE_SCALAR(IER);
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UNSERIALIZE_SCALAR(DLAB);
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UNSERIALIZE_SCALAR(LCR);
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UNSERIALIZE_SCALAR(MCR);
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Tick rxintrwhen;
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Tick txintrwhen;
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UNSERIALIZE_SCALAR(rxintrwhen);
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UNSERIALIZE_SCALAR(txintrwhen);
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if (rxintrwhen != 0)
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schedule(rxIntrEvent, rxintrwhen);
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if (txintrwhen != 0)
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schedule(txIntrEvent, txintrwhen);
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}
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Uart8250 *
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Uart8250Params::create()
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{
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return new Uart8250(this);
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}
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