52383ca7cc
cpu/ozone/cpu.hh:
Updates for sampler.
cpu/ozone/cpu_impl.hh:
Updates for sampler, checker.
cpu/ozone/inorder_back_end.hh:
Sampler updates. Also support old memory system.
--HG--
extra : convert_revision : 33ebe38e4c08d49c6af84032b819533b784b4fe8
522 lines
14 KiB
C++
522 lines
14 KiB
C++
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#ifndef __CPU_OZONE_LW_BACK_END_HH__
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#define __CPU_OZONE_LW_BACK_END_HH__
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#include <list>
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#include <queue>
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#include <set>
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#include <string>
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#include "arch/faults.hh"
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#include "base/timebuf.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/ozone/rename_table.hh"
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#include "cpu/ozone/thread_state.hh"
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#include "mem/functional/functional.hh"
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#include "mem/mem_interface.hh"
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#include "mem/mem_req.hh"
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#include "sim/eventq.hh"
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template <class>
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class Checker;
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class ExecContext;
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template <class Impl>
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class OzoneThreadState;
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template <class Impl>
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class LWBackEnd
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{
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public:
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typedef OzoneThreadState<Impl> Thread;
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::FrontEnd FrontEnd;
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typedef typename Impl::FullCPU::CommStruct CommStruct;
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struct SizeStruct {
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int size;
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};
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typedef SizeStruct DispatchToIssue;
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typedef SizeStruct IssueToExec;
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typedef SizeStruct ExecToCommit;
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typedef SizeStruct Writeback;
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TimeBuffer<DispatchToIssue> d2i;
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typename TimeBuffer<DispatchToIssue>::wire instsToDispatch;
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TimeBuffer<IssueToExec> i2e;
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typename TimeBuffer<IssueToExec>::wire instsToExecute;
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TimeBuffer<ExecToCommit> e2c;
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TimeBuffer<Writeback> numInstsToWB;
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TimeBuffer<CommStruct> *comm;
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typename TimeBuffer<CommStruct>::wire toIEW;
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typename TimeBuffer<CommStruct>::wire fromCommit;
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class TrapEvent : public Event {
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private:
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LWBackEnd<Impl> *be;
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public:
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TrapEvent(LWBackEnd<Impl> *_be);
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void process();
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const char *description();
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};
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/** LdWriteback event for a load completion. */
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class LdWritebackEvent : public Event {
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private:
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/** Instruction that is writing back data to the register file. */
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DynInstPtr inst;
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/** Pointer to IEW stage. */
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LWBackEnd *be;
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bool dcacheMiss;
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public:
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/** Constructs a load writeback event. */
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LdWritebackEvent(DynInstPtr &_inst, LWBackEnd *be);
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/** Processes writeback event. */
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virtual void process();
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/** Returns the description of the writeback event. */
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virtual const char *description();
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void setDcacheMiss() { dcacheMiss = true; be->addDcacheMiss(inst); }
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};
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LWBackEnd(Params *params);
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std::string name() const;
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void regStats();
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void setCPU(FullCPU *cpu_ptr);
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void setFrontEnd(FrontEnd *front_end_ptr)
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{ frontEnd = front_end_ptr; }
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void setXC(ExecContext *xc_ptr)
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{ xc = xc_ptr; }
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void setThreadState(Thread *thread_ptr)
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{ thread = thread_ptr; }
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void setCommBuffer(TimeBuffer<CommStruct> *_comm);
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void tick();
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void squash();
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void generateXCEvent() { xcSquash = true; }
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void squashFromXC();
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void squashFromTrap();
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void checkInterrupts();
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bool trapSquash;
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bool xcSquash;
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template <class T>
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Fault read(MemReqPtr &req, T &data, int load_idx);
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template <class T>
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Fault write(MemReqPtr &req, T &data, int store_idx);
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Addr readCommitPC() { return commitPC; }
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Addr commitPC;
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Tick lastCommitCycle;
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bool robEmpty() { return instList.empty(); }
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bool isFull() { return numInsts >= numROBEntries; }
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bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
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void fetchFault(Fault &fault);
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int wakeDependents(DynInstPtr &inst, bool memory_deps = false);
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/** Tells memory dependence unit that a memory instruction needs to be
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* rescheduled. It will re-execute once replayMemInst() is called.
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*/
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void rescheduleMemInst(DynInstPtr &inst);
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/** Re-executes all rescheduled memory instructions. */
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void replayMemInst(DynInstPtr &inst);
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/** Completes memory instruction. */
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void completeMemInst(DynInstPtr &inst) { }
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void addDcacheMiss(DynInstPtr &inst)
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{
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waitingMemOps.insert(inst->seqNum);
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numWaitingMemOps++;
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DPRINTF(BE, "Adding a Dcache miss mem op [sn:%lli], total %i\n",
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inst->seqNum, numWaitingMemOps);
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}
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void removeDcacheMiss(DynInstPtr &inst)
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{
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assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
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waitingMemOps.erase(inst->seqNum);
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numWaitingMemOps--;
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DPRINTF(BE, "Removing a Dcache miss mem op [sn:%lli], total %i\n",
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inst->seqNum, numWaitingMemOps);
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}
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void addWaitingMemOp(DynInstPtr &inst)
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{
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waitingMemOps.insert(inst->seqNum);
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numWaitingMemOps++;
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DPRINTF(BE, "Adding a waiting mem op [sn:%lli], total %i\n",
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inst->seqNum, numWaitingMemOps);
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}
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void removeWaitingMemOp(DynInstPtr &inst)
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{
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assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
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waitingMemOps.erase(inst->seqNum);
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numWaitingMemOps--;
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DPRINTF(BE, "Removing a waiting mem op [sn:%lli], total %i\n",
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inst->seqNum, numWaitingMemOps);
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}
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void instToCommit(DynInstPtr &inst);
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void switchOut();
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void doSwitchOut();
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void takeOverFrom(ExecContext *old_xc = NULL);
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bool isSwitchedOut() { return switchedOut; }
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private:
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void generateTrapEvent(Tick latency = 0);
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void handleFault(Fault &fault, Tick latency = 0);
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void updateStructures();
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void dispatchInsts();
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void dispatchStall();
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void checkDispatchStatus();
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void executeInsts();
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void commitInsts();
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void addToLSQ(DynInstPtr &inst);
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void writebackInsts();
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bool commitInst(int inst_num);
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void squash(const InstSeqNum &sn);
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void squashDueToBranch(DynInstPtr &inst);
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void squashDueToMemViolation(DynInstPtr &inst);
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void squashDueToMemBlocked(DynInstPtr &inst);
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void updateExeInstStats(DynInstPtr &inst);
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void updateComInstStats(DynInstPtr &inst);
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public:
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FullCPU *cpu;
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FrontEnd *frontEnd;
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ExecContext *xc;
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Thread *thread;
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enum Status {
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Running,
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Idle,
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DcacheMissStall,
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DcacheMissComplete,
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Blocked,
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TrapPending
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};
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Status status;
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Status dispatchStatus;
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Status commitStatus;
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Counter funcExeInst;
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private:
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// typedef typename Impl::InstQueue InstQueue;
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// InstQueue IQ;
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typedef typename Impl::LdstQueue LdstQueue;
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LdstQueue LSQ;
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public:
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RenameTable<Impl> commitRenameTable;
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RenameTable<Impl> renameTable;
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private:
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class DCacheCompletionEvent : public Event
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{
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private:
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LWBackEnd *be;
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public:
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DCacheCompletionEvent(LWBackEnd *_be);
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virtual void process();
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virtual const char *description();
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};
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friend class DCacheCompletionEvent;
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DCacheCompletionEvent cacheCompletionEvent;
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MemInterface *dcacheInterface;
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MemReqPtr memReq;
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// General back end width. Used if the more specific isn't given.
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int width;
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// Dispatch width.
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int dispatchWidth;
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int numDispatchEntries;
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int dispatchSize;
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int waitingInsts;
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int issueWidth;
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// Writeback width
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int wbWidth;
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// Commit width
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int commitWidth;
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/** Index into queue of instructions being written back. */
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unsigned wbNumInst;
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/** Cycle number within the queue of instructions being written
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* back. Used in case there are too many instructions writing
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* back at the current cycle and writesbacks need to be scheduled
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* for the future. See comments in instToCommit().
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*/
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unsigned wbCycle;
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int numROBEntries;
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int numInsts;
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std::set<InstSeqNum> waitingMemOps;
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typedef std::set<InstSeqNum>::iterator MemIt;
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int numWaitingMemOps;
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unsigned maxOutstandingMemOps;
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bool squashPending;
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InstSeqNum squashSeqNum;
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Addr squashNextPC;
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Fault faultFromFetch;
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bool fetchHasFault;
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bool switchedOut;
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bool switchPending;
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DynInstPtr memBarrier;
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private:
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struct pqCompare {
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bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
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{
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return lhs->seqNum > rhs->seqNum;
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}
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};
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typedef typename std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> ReadyInstQueue;
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ReadyInstQueue exeList;
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typedef typename std::list<DynInstPtr>::iterator InstListIt;
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std::list<DynInstPtr> instList;
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std::list<DynInstPtr> waitingList;
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std::list<DynInstPtr> replayList;
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std::list<DynInstPtr> writeback;
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int latency;
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int squashLatency;
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bool exactFullStall;
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// bool fetchRedirect[Impl::MaxThreads];
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// number of cycles stalled for D-cache misses
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/* Stats::Scalar<> dcacheStallCycles;
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Counter lastDcacheStall;
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*/
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Stats::Vector<> rob_cap_events;
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Stats::Vector<> rob_cap_inst_count;
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Stats::Vector<> iq_cap_events;
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Stats::Vector<> iq_cap_inst_count;
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// total number of instructions executed
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Stats::Vector<> exe_inst;
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Stats::Vector<> exe_swp;
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Stats::Vector<> exe_nop;
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Stats::Vector<> exe_refs;
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Stats::Vector<> exe_loads;
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Stats::Vector<> exe_branches;
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Stats::Vector<> issued_ops;
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// total number of loads forwaded from LSQ stores
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Stats::Vector<> lsq_forw_loads;
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// total number of loads ignored due to invalid addresses
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Stats::Vector<> inv_addr_loads;
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// total number of software prefetches ignored due to invalid addresses
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Stats::Vector<> inv_addr_swpfs;
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// ready loads blocked due to memory disambiguation
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Stats::Vector<> lsq_blocked_loads;
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Stats::Scalar<> lsqInversion;
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Stats::Vector<> n_issued_dist;
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Stats::VectorDistribution<> issue_delay_dist;
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Stats::VectorDistribution<> queue_res_dist;
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/*
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Stats::Vector<> stat_fu_busy;
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Stats::Vector2d<> stat_fuBusy;
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Stats::Vector<> dist_unissued;
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Stats::Vector2d<> stat_issued_inst_type;
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Stats::Formula misspec_cnt;
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Stats::Formula misspec_ipc;
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Stats::Formula issue_rate;
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Stats::Formula issue_stores;
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Stats::Formula issue_op_rate;
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Stats::Formula fu_busy_rate;
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Stats::Formula commit_stores;
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Stats::Formula commit_ipc;
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Stats::Formula commit_ipb;
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Stats::Formula lsq_inv_rate;
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*/
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Stats::Vector<> writeback_count;
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Stats::Vector<> producer_inst;
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Stats::Vector<> consumer_inst;
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Stats::Vector<> wb_penalized;
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Stats::Formula wb_rate;
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Stats::Formula wb_fanout;
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Stats::Formula wb_penalized_rate;
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// total number of instructions committed
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Stats::Vector<> stat_com_inst;
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Stats::Vector<> stat_com_swp;
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Stats::Vector<> stat_com_refs;
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Stats::Vector<> stat_com_loads;
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Stats::Vector<> stat_com_membars;
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Stats::Vector<> stat_com_branches;
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Stats::Distribution<> n_committed_dist;
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Stats::Scalar<> commit_eligible_samples;
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Stats::Vector<> commit_eligible;
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Stats::Vector<> squashedInsts;
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Stats::Vector<> ROBSquashedInsts;
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Stats::Scalar<> ROB_fcount;
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Stats::Formula ROB_full_rate;
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Stats::Vector<> ROB_count; // cumulative ROB occupancy
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Stats::Formula ROB_occ_rate;
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Stats::VectorDistribution<> ROB_occ_dist;
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public:
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void dumpInsts();
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Checker<DynInstPtr> *checker;
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};
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template <class Impl>
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template <class T>
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Fault
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LWBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
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{
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/* memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = cpu->translateDataReadReq(memReq);
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// if we have a cache, do cache access too
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if (fault == NoFault && dcacheInterface) {
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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// Fix this hack for keeping funcExeInst correct with loads that
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// are executed twice.
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--funcExeInst;
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memReq->completionEvent = &cacheCompletionEvent;
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lastDcacheStall = curTick;
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// unscheduleTickEvent();
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// status = DcacheMissStall;
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DPRINTF(OzoneCPU, "Dcache miss stall!\n");
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} else {
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// do functional access
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fault = thread->mem->read(memReq, data);
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}
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}
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*/
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/*
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if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
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recordEvent("Uncached Read");
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*/
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return LSQ.read(req, data, load_idx);
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}
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template <class Impl>
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template <class T>
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Fault
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LWBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
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{
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/*
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = cpu->translateDataWriteReq(memReq);
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if (fault == NoFault && dcacheInterface) {
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memReq->cmd = Write;
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memcpy(memReq->data,(uint8_t *)&data,memReq->size);
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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memReq->completionEvent = &cacheCompletionEvent;
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lastDcacheStall = curTick;
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// unscheduleTickEvent();
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// status = DcacheMissStall;
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DPRINTF(OzoneCPU, "Dcache miss stall!\n");
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}
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}
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if (res && (fault == NoFault))
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*res = memReq->result;
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*/
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/*
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if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
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recordEvent("Uncached Write");
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*/
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return LSQ.write(req, data, store_idx);
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}
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#endif // __CPU_OZONE_LW_BACK_END_HH__
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