5df3e61f16
Dependecy graph code moved into its own class.
This requires the changes to the functional units, which is in the next check in.
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
IEW and IQ code cleanup and reorganization.
cpu/o3/inst_queue.cc:
Dependency graph code moved into its own class now.
cpu/o3/inst_queue.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
cpu/o3/inst_queue_impl.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
Issue loop cleaned up, with completion events for functional units now used more correctly (before they weren't used for multi-cycle ops with pipelined FU's).
--HG--
extra : convert_revision : 35e50192df6f71dc81d46a73fdd65f7ec07c10e4
476 lines
16 KiB
C++
476 lines
16 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_INST_QUEUE_HH__
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#define __CPU_O3_INST_QUEUE_HH__
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#include <list>
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#include <map>
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#include <queue>
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#include <vector>
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/dep_graph.hh"
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#include "encumbered/cpu/full/op_class.hh"
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#include "sim/host.hh"
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class FUPool;
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class MemInterface;
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/**
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* A standard instruction queue class. It holds ready instructions, in
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* order, in seperate priority queues to facilitate the scheduling of
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* instructions. The IQ uses a separate linked list to track dependencies.
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* Similar to the rename map and the free list, it expects that
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* floating point registers have their indices start after the integer
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* registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
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* and 96-191 are fp). This remains true even for both logical and
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* physical register indices. The IQ depends on the memory dependence unit to
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* track when memory operations are ready in terms of ordering; register
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* dependencies are tracked normally. Right now the IQ also handles the
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* execution timing; this is mainly to allow back-to-back scheduling without
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* requiring IEW to be able to peek into the IQ. At the end of the execution
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* latency, the instruction is put into the queue to execute, where it will
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* have the execute() function called on it.
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* @todo: Make IQ able to handle multiple FU pools.
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*/
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template <class Impl>
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class InstructionQueue
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{
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public:
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//Typedefs from the Impl.
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::Params Params;
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typedef typename Impl::CPUPol::IEW IEW;
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typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
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typedef typename Impl::CPUPol::IssueStruct IssueStruct;
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typedef typename Impl::CPUPol::TimeStruct TimeStruct;
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// Typedef of iterator through the list of instructions.
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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friend class Impl::FullCPU;
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/** FU completion event class. */
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class FUCompletion : public Event {
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private:
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/** Executing instruction. */
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DynInstPtr inst;
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/** Index of the FU used for executing. */
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int fuIdx;
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/** Pointer back to the instruction queue. */
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InstructionQueue<Impl> *iqPtr;
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bool freeFU;
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public:
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/** Construct a FU completion event. */
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FUCompletion(DynInstPtr &_inst, int fu_idx,
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InstructionQueue<Impl> *iq_ptr);
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virtual void process();
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virtual const char *description();
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void setFreeFU() { freeFU = true; }
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};
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/** Constructs an IQ. */
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InstructionQueue(Params *params);
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/** Destructs the IQ. */
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~InstructionQueue();
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/** Returns the name of the IQ. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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void resetState();
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/** Sets CPU pointer. */
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void setCPU(FullCPU *_cpu) { cpu = _cpu; }
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/** Sets active threads list. */
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void setActiveThreads(std::list<unsigned> *at_ptr);
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/** Sets the IEW pointer. */
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void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
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/** Sets the timer buffer between issue and execute. */
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void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
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/** Sets the global time buffer. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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void switchOut();
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void takeOverFrom();
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bool isSwitchedOut() { return switchedOut; }
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/** Number of entries needed for given amount of threads. */
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int entryAmount(int num_threads);
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/** Resets max entries for all threads. */
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void resetEntries();
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/** Returns total number of free entries. */
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unsigned numFreeEntries();
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/** Returns number of free entries for a thread. */
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unsigned numFreeEntries(unsigned tid);
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/** Returns whether or not the IQ is full. */
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bool isFull();
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/** Returns whether or not the IQ is full for a specific thread. */
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bool isFull(unsigned tid);
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/** Returns if there are any ready instructions in the IQ. */
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bool hasReadyInsts();
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/** Inserts a new instruction into the IQ. */
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void insert(DynInstPtr &new_inst);
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/** Inserts a new, non-speculative instruction into the IQ. */
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void insertNonSpec(DynInstPtr &new_inst);
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/** Inserts a memory or write barrier into the IQ to make sure
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* loads and stores are ordered properly.
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*/
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void insertBarrier(DynInstPtr &barr_inst);
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/**
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* Records the instruction as the producer of a register without
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* adding it to the rest of the IQ.
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*/
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void recordProducer(DynInstPtr &inst)
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{ addToProducers(inst); }
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/** Process FU completion event. */
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void processFUCompletion(DynInstPtr &inst, int fu_idx);
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/**
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* Schedules ready instructions, adding the ready ones (oldest first) to
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* the queue to execute.
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*/
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void scheduleReadyInsts();
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/** Schedules a single specific non-speculative instruction. */
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void scheduleNonSpec(const InstSeqNum &inst);
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/**
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* Commits all instructions up to and including the given sequence number,
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* for a specific thread.
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*/
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void commit(const InstSeqNum &inst, unsigned tid = 0);
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/** Wakes all dependents of a completed instruction. */
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int wakeDependents(DynInstPtr &completed_inst);
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/** Adds a ready memory instruction to the ready list. */
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void addReadyMemInst(DynInstPtr &ready_inst);
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/**
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* Reschedules a memory instruction. It will be ready to issue once
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* replayMemInst() is called.
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*/
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void rescheduleMemInst(DynInstPtr &resched_inst);
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/** Replays a memory instruction. It must be rescheduled first. */
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void replayMemInst(DynInstPtr &replay_inst);
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/** Completes a memory operation. */
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void completeMemInst(DynInstPtr &completed_inst);
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/** Indicates an ordering violation between a store and a load. */
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void violation(DynInstPtr &store, DynInstPtr &faulting_load);
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/**
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* Squashes instructions for a thread. Squashing information is obtained
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* from the time buffer.
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*/
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void squash(unsigned tid);
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/** Returns the number of used entries for a thread. */
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unsigned getCount(unsigned tid) { return count[tid]; };
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/** Debug function to print all instructions. */
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void printInsts();
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private:
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/** Does the actual squashing. */
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void doSquash(unsigned tid);
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/////////////////////////
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// Various pointers
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/////////////////////////
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/** Pointer to the CPU. */
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FullCPU *cpu;
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/** Cache interface. */
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MemInterface *dcacheInterface;
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/** Pointer to IEW stage. */
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IEW *iewStage;
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/** The memory dependence unit, which tracks/predicts memory dependences
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* between instructions.
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*/
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MemDepUnit memDepUnit[Impl::MaxThreads];
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/** The queue to the execute stage. Issued instructions will be written
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* into it.
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*/
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TimeBuffer<IssueStruct> *issueToExecuteQueue;
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/** The backwards time buffer. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to read information from timebuffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Function unit pool. */
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FUPool *fuPool;
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//////////////////////////////////////
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// Instruction lists, ready queues, and ordering
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//////////////////////////////////////
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/** List of all the instructions in the IQ (some of which may be issued). */
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std::list<DynInstPtr> instList[Impl::MaxThreads];
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/**
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* Struct for comparing entries to be added to the priority queue. This
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* gives reverse ordering to the instructions in terms of sequence
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* numbers: the instructions with smaller sequence numbers (and hence
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* are older) will be at the top of the priority queue.
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*/
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struct pqCompare {
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bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
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{
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return lhs->seqNum > rhs->seqNum;
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}
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};
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typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
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ReadyInstQueue;
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/** List of ready instructions, per op class. They are separated by op
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* class to allow for easy mapping to FUs.
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*/
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ReadyInstQueue readyInsts[Num_OpClasses];
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/** List of non-speculative instructions that will be scheduled
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* once the IQ gets a signal from commit. While it's redundant to
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* have the key be a part of the value (the sequence number is stored
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* inside of DynInst), when these instructions are woken up only
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* the sequence number will be available. Thus it is most efficient to be
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* able to search by the sequence number alone.
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*/
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std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
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typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
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/** Entry for the list age ordering by op class. */
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struct ListOrderEntry {
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OpClass queueType;
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InstSeqNum oldestInst;
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};
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/** List that contains the age order of the oldest instruction of each
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* ready queue. Used to select the oldest instruction available
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* among op classes.
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* @todo: Might be better to just move these entries around instead
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* of creating new ones every time the position changes due to an
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* instruction issuing. Not sure std::list supports this.
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*/
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std::list<ListOrderEntry> listOrder;
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typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
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/** Tracks if each ready queue is on the age order list. */
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bool queueOnList[Num_OpClasses];
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/** Iterators of each ready queue. Points to their spot in the age order
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* list.
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*/
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ListOrderIt readyIt[Num_OpClasses];
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/** Add an op class to the age order list. */
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void addToOrderList(OpClass op_class);
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/**
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* Called when the oldest instruction has been removed from a ready queue;
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* this places that ready queue into the proper spot in the age order list.
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*/
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void moveToYoungerInst(ListOrderIt age_order_it);
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DependencyGraph<DynInstPtr> dependGraph;
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//////////////////////////////////////
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// Various parameters
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//////////////////////////////////////
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/** IQ Resource Sharing Policy */
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enum IQPolicy {
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Dynamic,
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Partitioned,
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Threshold
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};
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/** IQ sharing policy for SMT. */
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IQPolicy iqPolicy;
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/** Number of Total Threads*/
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unsigned numThreads;
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/** Pointer to list of active threads. */
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std::list<unsigned> *activeThreads;
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/** Per Thread IQ count */
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unsigned count[Impl::MaxThreads];
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/** Max IQ Entries Per Thread */
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unsigned maxEntries[Impl::MaxThreads];
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/** Number of free IQ entries left. */
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unsigned freeEntries;
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/** The number of entries in the instruction queue. */
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unsigned numEntries;
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/** The total number of instructions that can be issued in one cycle. */
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unsigned totalWidth;
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/** The number of physical registers in the CPU. */
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unsigned numPhysRegs;
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/** The number of physical integer registers in the CPU. */
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unsigned numPhysIntRegs;
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/** The number of floating point registers in the CPU. */
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unsigned numPhysFloatRegs;
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/** Delay between commit stage and the IQ.
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* @todo: Make there be a distinction between the delays within IEW.
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*/
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unsigned commitToIEWDelay;
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bool switchedOut;
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/** The sequence number of the squashed instruction. */
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InstSeqNum squashedSeqNum[Impl::MaxThreads];
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/** A cache of the recently woken registers. It is 1 if the register
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* has been woken up recently, and 0 if the register has been added
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* to the dependency graph and has not yet received its value. It
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* is basically a secondary scoreboard, and should pretty much mirror
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* the scoreboard that exists in the rename map.
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*/
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std::vector<bool> regScoreboard;
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/** Adds an instruction to the dependency graph, as a consumer. */
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bool addToDependents(DynInstPtr &new_inst);
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/** Adds an instruction to the dependency graph, as a producer. */
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void addToProducers(DynInstPtr &new_inst);
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/** Moves an instruction to the ready queue if it is ready. */
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void addIfReady(DynInstPtr &inst);
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/** Debugging function to count how many entries are in the IQ. It does
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* a linear walk through the instructions, so do not call this function
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* during normal execution.
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*/
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int countInsts();
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/** Debugging function to dump all the list sizes, as well as print
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* out the list of nonspeculative instructions. Should not be used
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* in any other capacity, but it has no harmful sideaffects.
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*/
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void dumpLists();
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/** Debugging function to dump out all instructions that are in the
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* IQ.
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*/
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void dumpInsts();
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/** Stat for number of instructions added. */
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Stats::Scalar<> iqInstsAdded;
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/** Stat for number of non-speculative instructions added. */
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Stats::Scalar<> iqNonSpecInstsAdded;
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Stats::Scalar<> iqInstsIssued;
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/** Stat for number of integer instructions issued. */
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Stats::Scalar<> iqIntInstsIssued;
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/** Stat for number of floating point instructions issued. */
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Stats::Scalar<> iqFloatInstsIssued;
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/** Stat for number of branch instructions issued. */
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Stats::Scalar<> iqBranchInstsIssued;
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/** Stat for number of memory instructions issued. */
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Stats::Scalar<> iqMemInstsIssued;
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/** Stat for number of miscellaneous instructions issued. */
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Stats::Scalar<> iqMiscInstsIssued;
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/** Stat for number of squashed instructions that were ready to issue. */
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Stats::Scalar<> iqSquashedInstsIssued;
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/** Stat for number of squashed instructions examined when squashing. */
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Stats::Scalar<> iqSquashedInstsExamined;
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/** Stat for number of squashed instruction operands examined when
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* squashing.
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*/
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Stats::Scalar<> iqSquashedOperandsExamined;
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/** Stat for number of non-speculative instructions removed due to a squash.
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*/
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Stats::Scalar<> iqSquashedNonSpecRemoved;
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Stats::VectorDistribution<> queueResDist;
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Stats::Distribution<> numIssuedDist;
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Stats::VectorDistribution<> issueDelayDist;
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Stats::Vector<> statFuBusy;
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// Stats::Vector<> dist_unissued;
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Stats::Vector2d<> statIssuedInstType;
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Stats::Formula issueRate;
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// Stats::Formula issue_stores;
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// Stats::Formula issue_op_rate;
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Stats::Vector<> fuBusy; //cumulative fu busy
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Stats::Formula fuBusyRate;
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};
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#endif //__CPU_O3_INST_QUEUE_HH__
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