ef6e2eb3c4
cpu/o3/alpha_cpu.hh:
Update for sampler to work properly. Also code cleanup.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.hh:
Updates to support the checker.
cpu/o3/alpha_cpu_impl.hh:
Updates to support the checker. Also general code cleanup.
cpu/o3/alpha_dyn_inst_impl.hh:
Code cleanup.
cpu/o3/alpha_params.hh:
Updates to support the checker. Also supports trap latencies set through the parameters.
cpu/o3/commit.hh:
Supports sampler, checker. Code cleanup.
cpu/o3/commit_impl.hh:
Updates to support the sampler and checker, as well as general code cleanup.
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Support sampler and checker.
cpu/o3/decode_impl.hh:
Supports sampler.
cpu/o3/fetch.hh:
Supports sampler. Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained.
cpu/o3/fetch_impl.hh:
Sampler updates. Also be sure to not fetches to uncached space (bad path).
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
Sampler updates.
cpu/o3/lsq_unit_impl.hh:
Supports checker.
cpu/o3/regfile.hh:
No need for accessing xcProxies directly.
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
Sampler support.
--HG--
extra : convert_revision : 03881885dd50ebbca13ef31f31492fd4ef59121c
416 lines
13 KiB
C++
416 lines
13 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_FETCH_HH__
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#define __CPU_O3_FETCH_HH__
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/pc_event.hh"
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#include "mem/mem_interface.hh"
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#include "sim/eventq.hh"
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class Sampler;
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/**
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* DefaultFetch class handles both single threaded and SMT fetch. Its width is
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* specified by the parameters; each cycle it tries to fetch that many
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* instructions. It supports using a branch predictor to predict direction and
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* targets.
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* It supports the idling functionalitiy of the CPU by indicating to the CPU
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* when it is active and inactive.
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*/
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template <class Impl>
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class DefaultFetch
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{
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public:
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/** Typedefs from Impl. */
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typedef typename Impl::CPUPol CPUPol;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::Params Params;
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/** Typedefs from the CPU policy. */
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typedef typename CPUPol::BPredUnit BPredUnit;
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typedef typename CPUPol::FetchStruct FetchStruct;
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typedef typename CPUPol::TimeStruct TimeStruct;
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/** Typedefs from ISA. */
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typedef TheISA::MachInst MachInst;
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typedef TheISA::ExtMachInst ExtMachInst;
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public:
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/** Overall fetch status. Used to determine if the CPU can deschedule itsef
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* due to a lack of activity.
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*/
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enum FetchStatus {
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Active,
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Inactive
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};
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/** Individual thread status. */
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enum ThreadStatus {
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Running,
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Idle,
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Squashing,
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Blocked,
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Fetching,
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TrapPending,
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QuiescePending,
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SwitchOut,
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IcacheMissStall,
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IcacheMissComplete
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};
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/** Fetching Policy, Add new policies here.*/
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enum FetchPriority {
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SingleThread,
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RoundRobin,
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Branch,
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IQ,
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LSQ
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};
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private:
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/** Fetch status. */
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FetchStatus _status;
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/** Per-thread status. */
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ThreadStatus fetchStatus[Impl::MaxThreads];
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/** Fetch policy. */
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FetchPriority fetchPolicy;
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/** List that has the threads organized by priority. */
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std::list<unsigned> priorityList;
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public:
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class CacheCompletionEvent : public Event
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{
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private:
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MemReqPtr req;
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/** Pointer to fetch. */
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DefaultFetch *fetch;
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/** Thread id. */
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// unsigned threadId;
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public:
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/** Constructs a cache completion event, which tells fetch when the
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* cache miss is complete.
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*/
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CacheCompletionEvent(MemReqPtr &_req, DefaultFetch *_fetch);
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/** Processes cache completion event. */
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virtual void process();
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/** Returns the description of the cache completion event. */
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virtual const char *description();
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};
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public:
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/** DefaultFetch constructor. */
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DefaultFetch(Params *params);
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/** Returns the name of fetch. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Sets CPU pointer. */
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void setCPU(FullCPU *cpu_ptr);
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/** Sets the main backwards communication time buffer pointer. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
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/** Sets pointer to list of active threads. */
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void setActiveThreads(std::list<unsigned> *at_ptr);
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/** Sets pointer to time buffer used to communicate to the next stage. */
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void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
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/** Sets pointer to page table. */
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// void setPageTable(PageTable *pt_ptr);
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/** Initialize stage. */
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void initStage();
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/** Processes cache completion event. */
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void processCacheCompletion(MemReqPtr &req);
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void switchOut();
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void doSwitchOut();
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void takeOverFrom();
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bool isSwitchedOut() { return switchedOut; }
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void wakeFromQuiesce();
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private:
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/** Changes the status of this stage to active, and indicates this to the
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* CPU.
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*/
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inline void switchToActive();
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/** Changes the status of this stage to inactive, and indicates this to the
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* CPU.
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*/
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inline void switchToInactive();
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/**
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* Looks up in the branch predictor to see if the next PC should be
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* either next PC+=MachInst or a branch target.
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* @param next_PC Next PC variable passed in by reference. It is
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* expected to be set to the current PC; it will be updated with what
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* the next PC will be.
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* @return Whether or not a branch was predicted as taken.
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*/
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bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
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/**
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* Fetches the cache line that contains fetch_PC. Returns any
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* fault that happened. Puts the data into the class variable
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* cacheData.
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* @param fetch_PC The PC address that is being fetched from.
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* @param ret_fault The fault reference that will be set to the result of
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* the icache access.
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* @param tid Thread id.
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* @return Any fault that occured.
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*/
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bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
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/** Squashes a specific thread and resets the PC. */
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inline void doSquash(const Addr &new_PC, unsigned tid);
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/** Squashes a specific thread and resets the PC. Also tells the CPU to
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* remove any instructions between fetch and decode that should be sqaushed.
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*/
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void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
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unsigned tid);
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/** Checks if a thread is stalled. */
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bool checkStall(unsigned tid) const;
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/** Updates overall fetch stage status; to be called at the end of each
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* cycle. */
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FetchStatus updateFetchStatus();
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public:
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/** Squashes a specific thread and resets the PC. Also tells the CPU to
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* remove any instructions that are not in the ROB. The source of this
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* squash should be the commit stage.
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*/
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void squash(const Addr &new_PC, unsigned tid);
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/** Ticks the fetch stage, processing all inputs signals and fetching
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* as many instructions as possible.
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*/
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void tick();
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/** Checks all input signals and updates the status as necessary.
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* @return: Returns if the status has changed due to input signals.
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*/
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bool checkSignalsAndUpdate(unsigned tid);
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/** Does the actual fetching of instructions and passing them on to the
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* next stage.
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* @param status_change fetch() sets this variable if there was a status
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* change (ie switching to IcacheMissStall).
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*/
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void fetch(bool &status_change);
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/** Align a PC to the start of an I-cache block. */
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Addr icacheBlockAlignPC(Addr addr)
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{
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addr = TheISA::realPCToFetchPC(addr);
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return (addr & ~(cacheBlkMask));
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}
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private:
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/** Returns the appropriate thread to fetch, given the fetch policy. */
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int getFetchingThread(FetchPriority &fetch_priority);
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/** Returns the appropriate thread to fetch using a round robin policy. */
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int roundRobin();
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/** Returns the appropriate thread to fetch using the IQ count policy. */
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int iqCount();
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/** Returns the appropriate thread to fetch using the LSQ count policy. */
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int lsqCount();
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/** Returns the appropriate thread to fetch using the branch count policy. */
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int branchCount();
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private:
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/** Pointer to the FullCPU. */
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FullCPU *cpu;
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to get decode's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromDecode;
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/** Wire to get rename's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromRename;
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/** Wire to get iew's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromIEW;
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/** Wire to get commit's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Internal fetch instruction queue. */
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TimeBuffer<FetchStruct> *fetchQueue;
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//Might be annoying how this name is different than the queue.
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/** Wire used to write any information heading to decode. */
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typename TimeBuffer<FetchStruct>::wire toDecode;
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/** Icache interface. */
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MemInterface *icacheInterface;
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/** BPredUnit. */
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BPredUnit branchPred;
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Addr PC[Impl::MaxThreads];
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Addr nextPC[Impl::MaxThreads];
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/** Memory request used to access cache. */
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MemReqPtr memReq[Impl::MaxThreads];
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/** Variable that tracks if fetch has written to the time buffer this
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* cycle. Used to tell CPU if there is activity this cycle.
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*/
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bool wroteToTimeBuffer;
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/** Tracks how many instructions has been fetched this cycle. */
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int numInst;
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/** Source of possible stalls. */
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struct Stalls {
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bool decode;
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bool rename;
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bool iew;
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bool commit;
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};
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/** Tracks which stages are telling fetch to stall. */
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Stalls stalls[Impl::MaxThreads];
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/** Decode to fetch delay, in ticks. */
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unsigned decodeToFetchDelay;
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/** Rename to fetch delay, in ticks. */
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unsigned renameToFetchDelay;
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/** IEW to fetch delay, in ticks. */
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unsigned iewToFetchDelay;
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/** Commit to fetch delay, in ticks. */
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unsigned commitToFetchDelay;
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/** The width of fetch in instructions. */
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unsigned fetchWidth;
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/** Cache block size. */
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int cacheBlkSize;
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/** Mask to get a cache block's address. */
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Addr cacheBlkMask;
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/** The cache line being fetched. */
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uint8_t *cacheData[Impl::MaxThreads];
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/** Size of instructions. */
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int instSize;
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/** Icache stall statistics. */
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Counter lastIcacheStall[Impl::MaxThreads];
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/** List of Active Threads */
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std::list<unsigned> *activeThreads;
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/** Number of threads. */
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unsigned numThreads;
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/** Number of threads that are actively fetching. */
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unsigned numFetchingThreads;
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/** Thread ID being fetched. */
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int threadFetched;
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bool interruptPending;
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bool switchedOut;
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public:
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InstSeqNum &getYoungestSN() { return youngestSN; }
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private:
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InstSeqNum youngestSN;
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#if !FULL_SYSTEM
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/** Page table pointer. */
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// PageTable *pTable;
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#endif
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// @todo: Consider making these vectors and tracking on a per thread basis.
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/** Stat for total number of cycles stalled due to an icache miss. */
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Stats::Scalar<> icacheStallCycles;
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/** Stat for total number of fetched instructions. */
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Stats::Scalar<> fetchedInsts;
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Stats::Scalar<> fetchedBranches;
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/** Stat for total number of predicted branches. */
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Stats::Scalar<> predictedBranches;
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/** Stat for total number of cycles spent fetching. */
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Stats::Scalar<> fetchCycles;
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/** Stat for total number of cycles spent squashing. */
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Stats::Scalar<> fetchSquashCycles;
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/** Stat for total number of cycles spent blocked due to other stages in
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* the pipeline.
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*/
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Stats::Scalar<> fetchIdleCycles;
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Stats::Scalar<> fetchBlockedCycles;
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Stats::Scalar<> fetchMiscStallCycles;
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/** Stat for total number of fetched cache lines. */
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Stats::Scalar<> fetchedCacheLines;
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Stats::Scalar<> fetchIcacheSquashes;
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/** Distribution of number of instructions fetched each cycle. */
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Stats::Distribution<> fetchNisnDist;
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Stats::Formula idleRate;
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Stats::Formula branchRate;
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Stats::Formula fetchRate;
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};
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#endif //__CPU_O3_FETCH_HH__
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