gem5/src/arch
Andreas Sandberg 5d584934ad x86: Make fprem like the fprem on a real x87
The current implementation of fprem simply does an fmod and doesn't
simulate any of the iterative behavior in a real fprem. This isn't
normally a problem, however, it can lead to problems when switching
between CPU models. If switching from a real CPU in the middle of an
fprem loop to a simulated CPU, the output of the fprem loop becomes
correupted. This changeset changes the fprem implementation to work
like the one on real hardware.
2013-06-18 16:10:42 +02:00
..
alpha arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
arm arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
generic arch: Fix broken M5VarArgsFault initialization 2013-01-07 13:05:38 -05:00
mips arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
noisa cpu: add separate stats for insts/ops both globally and per cpu model 2012-02-12 16:07:39 -06:00
power arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
sparc arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
x86 x86: Make fprem like the fprem on a real x87 2013-06-18 16:10:42 +02:00
isa_parser.py O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript CPU: Merge the predecoder and decoder. 2012-05-26 13:44:46 -07:00